For Communications Equipment
MN86062
CODEC LSI for Facsimile Images
Overview
The MN86062 is a high-speed LSI codec for compressing
and decompressing images using the MH, MR, and MMR
standard compression methods specified in the ITU-T T.4
and T.6 recommendation. Registers and other settings
provide flexible support for a variety of processing.
Features
Compression methods
MH, MR, and MMR
Operating mode:
Page mode
Bus configuration:
Choice of dual- or single-bus operation
Decoding error processing:
Choice of replacing with the previous line or a
white line
Image bus configuration:
8 bits, maximum 16 megabytes address
space of image bus, 2-channel master DMA
System bus configuration:
X80 interface compatible, 8 bits, 2-channel
slave DMA
Pixels per line:
maximum 64K, in byte increments
Concurrent DMA transfers over image bus and
command processing
Support for pointer management for image buffer
Wide selection of independent parameters for coding,
decoding, transfers between buses, and DMA
transfersr
Support for time-shared processing by line for both
coding and decoding
Applications
Facsimile equipment
MN86062
Pin Assignment
For Communications Equipment
V
SS2
V
DD2
TACK
V
SS3
V
DD3
N.C.3
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
V
DD4
V
SS4
TEST2
TEST1
TEST0
NACKD
NACKC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
N.C.1
N.C.2
IA18
IA17
IA16
IA15
IA14
IA13
IA12
IA11
IA10
IA9
IA8
IA7
IA6
IA5
IA4
IA3
IA2
IA1
IA0
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
IA19
IA20
IA21
IA22
IA23
NDCMP
NDEND
NDACK1
NDACK0
NDREQ1
NDREQ0
NIDACK
IR/W
NIAEN
NDRUN
NIBACK
NIBREQ
2SYSCLK
V
DD1
V
SS1
SYSCLK
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
TEST3
TEST4
D0
D1
D2
D3
D4
D5
D6
D7
NIRQ
NRESET
A0
A1
A2
A3
NCS
NRD
NWT
NREQC
NREQD
(TOP VIEW)
QFP084-P-1818
Microprogram control block
IA(23:0)
Main sequencer
Sub sequencer
51
IR/W
50
Image bus interface
52
47
ALU1
Register bank
Parameter register
53
55
54
Master DMA
(2 channels)
Table look-up block
Mode selection block
56
NDACK1
49
57
58
Reference line FIFO
Coding table
Change point
detector
Coding line FIFO
Image
reconstruction
block
NDRUN
NDEND
NDCMP
NDREQ0
NDACK0
NDREQ1
ALU2
48
NIAEN
NIDACK
NIBREQ
NIBACK
ID(7:0)
Block Diagram
A(3:0)
D(7:0)
System bus
interface
NCS
NRD
25
NWT
24
32
NIRQ
For Communications Equipment
NRESET
31
2SYSCLK
46
SYSCLK
43
NREQC
23
NACKC
21
Slave DMA
(2 channels)
NREQD
22
NACKD
20
Coding FIFO
Decoding FIFO
Decoding table
V
DD
V
SS
MN86062
TEST(4:0)
MN86062
Pin Descriptions
System Bus Interface
Pin No.
27
28
29
30
33
34
35
36
37
38
39
40
24
25
26
23
22
21
20
32
31
46
43
15
5
2
45
16
4
1
44
41
42
17
18
19
3
Symbol
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
NWT
NRD
NCS
NREQC
NREQD
NACKC
NACKD
NIRQ
NRESET
2SYSCLK
SYSCLK
V
DD4
V
DD3
V
DD2
V
DD1
V
SS4
V
SS3
V
SS2
V
SS1
TEST4
TEST3
TEST2
TEST1
TEST0
TACK
O
Do not use these test pins.
I
Do not use these test pins.
I
I
I
I
O
Tristate
O
Tristate
I
I
O
Open drain
I
I
O
I
I/O
Tristate
I/O
I
For Communications Equipment
Function Description
Address bus for accessing internal registers
Data bus for bidirectional transfers over system bus
Connect to WR pin on X80-compatible microprocessor
Connect to RD pin on X80-compatible microprocessor
Chip select pin
This output pin indicates a DMA transfer request from the 86062 to
memory.
This output pin indicates a DMA transfer request from the memory to
86062.
This input pin accepts the response to the NREQC signal.
This input pin accepts the response to the NREQD signal.
This output pin indicates an interrupt request.
External input resets the 86062.
This input pin accepts a clock signal with twice the system clock frequency.
This output pin provides a clock signal with half the frequency of 2SYSCLK.
Connect these power supply pins to a 5 volt power supply.
Connect these power supply pins to ground.
For Communications Equipment
Pin Descriptions (continued)
Image Bus Interface (continued)
Pin No.
59
60
61
62
63
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
7
8
9
10
11
12
13
14
47
48
50
51
Symbol
IA23
IA22
IA21
IA20
IA19
IA18
IA17
IA16
IA15
IA14
IA13
IA12
IA11
IA10
IA9
IA8
IA7
IA6
IA5
IA4
IA3
IA2
IA1
IA0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
IBREQ
IBACK
IAEN
IR/W
O
I
O
Tristate
O
Tristate
I/O
Tristate
Image data bus for bidirectional transfers of image data
I/O
O
Tristate
MN86062
Function Description
Image address bus. The address is valid when the NIAEN pin is at "L"
level.
This output pin indicates a request for control of the image bus.
This input pin accepts the response to the NIBREQ signal.
This output pin indicates whether the values of image address bus are
valid.
This output pin indicates the data transfer direction for the image bus.
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