AD9257-65EBZ datasheet, PDF - EEWORLD Datasheet

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AD9257-65EBZ: DescriptionAnalog to Digital Converters - ADC Octal 14-Bit 65 MSPS Serial LVDS 1.8V; CategoryDevelopment board/suite/development tools; File Size1MB，41 Pages; ManufacturerADI; Websitehttps://www.analog.com

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AD9257-65EBZ Overview

Analog to Digital Converters - ADC Octal 14-Bit 65 MSPS Serial LVDS 1.8V

AD9257-65EBZ Parametric

Parameter Name	Attribute value
Product Category	Data Conversion IC Development Tools
Manufacturer	ADI
RoHS	Details
Product	Evaluation Boards
Type	ADC
Tool Is For Evaluation Of	AD9257
Operating Supply Voltage	1.7 V to 1.9 V
Packaging	Bulk
Description/Function	Evaluation board for the AD9257
For Use With	AD9257
Interface Type	Serial
Maximum Operating Temperature	+ 85 C
Minimum Operating Temperature	- 40 C
Operating Supply Current	198 mA
Factory Pack Quantity	1
Unit Weight	8.818490 oz

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Data Sheet

FEATURES

Octal, 14-Bit, 40/65 MSPS, Serial LVDS,

1.8 V Analog-to-Digital Converter

AD9257

FUNCTIONAL BLOCK DIAGRAM

AVDD

PDWN

ADC

VIN+ B

VIN– B

VIN+ C

VIN– C

VIN+ D

VIN– D

VIN+ E

VIN– E

VIN+ F

VIN– F

VIN+ G

VIN– G

VIN+ H

VIN– H

VREF

SENSE

VCM

SYNC

RBIAS

AGND

CSB

SDIO/ SCLK/

DFS

DTP

CLK+ CLK–

REF

SELECT

1.0V

SERIAL PORT

INTERFACE

DATA

RATE

MULTIPLIER

FCO+

FCO–

DCO+

DCO–

10206-001

Low power: 55 mW per channel at 65 MSPS with scalable

power options

SNR = 75.5 dB (to Nyquist)

SFDR = 91.6 dBc (to Nyquist)

DNL = ±0.6 LSB (typical), INL = ±1.1 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power, reduced signal option (similar to IEEE 1596.3)

Data and frame clock outputs

650 MHz full power analog bandwidth

2 V p-p input voltage range

1.8 V supply operation

Serial port control

Full chip and individual channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

DRVDD

AD9257

VIN+ A

VIN– A

SERIAL

LVDS

D+ A

D– A

D+ B

D– B

D+ C

D– C

D+ D

D– D

D+ E

D– E

D+ F

D– F

D+ G

D– G

D+ H

D– H

ADC

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

APPLICATIONS

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam-forming systems

Quadrature radio receivers

Diversity radio receivers

Optical networking

Test equipment

Figure 1.

GENERAL DESCRIPTION

The

AD9257

is an octal, 14-bit, 40 MSPS and 65 MSPS analog-

to-digital converter (ADC) with an on-chip sample-and-hold

circuit designed for low cost, low power, small size, and ease of

use. The product operates at a conversion rate of up to 65 MSPS

and is optimized for outstanding dynamic performance and low

power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

The ADC automatically multiplies the sample rate clock for the

appropriate LVDS serial data rate. A data clock output (DCO) for

capturing data on the output and a frame clock output (FCO) for

signaling a new output byte are provided. Individual channel

power-down is supported and typically consumes less than

2 mW when all channels are disabled.

The ADC contains several features designed to maximize flexibility

and minimize system cost, such as programmable clock and data

Rev. A

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

alignment and programmable digital test pattern generation. The

available digital test patterns include built-in deterministic and

pseudorandom patterns, along with custom user-defined test

patterns entered via the serial port interface (SPI).

The

AD9257

is available in an RoHS-compliant, 64-lead LFCSP.

It is specified over the industrial temperature range of −40°C

to +85°C. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

Small Footprint. Eight ADCs are contained in a small,

space-saving package.

Low Power of 55 mW/Channel at 65 MSPS with Scalable

Power Options.

Ease of Use. A data clock output (DCO) is provided that

operates at frequencies of up to 455 MHz and supports

double data rate (DDR) operation.

User Flexibility. The SPI control offers a wide range of

flexible features to meet specific system requirements.

Pin Compatible with the

AD9637

(12-Bit Octal ADC).

AD9257

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 8

Thermal Characteristics .............................................................. 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 11

AD9257-65 .................................................................................. 11

AD9257-40 .................................................................................. 14

Equivalent Circuits ......................................................................... 17

Theory of Operation ...................................................................... 18

Analog Input Considerations.................................................... 18

Voltage Reference ....................................................................... 19

Clock Input Considerations ...................................................... 20

Data Sheet

Power Dissipation and Power-Down Mode ........................... 22

Digital Outputs and Timing ..................................................... 23

Built-In Output Test Modes .......................................................... 27

Output Test Modes ..................................................................... 27

Serial Port Interface (SPI) .............................................................. 28

Configuration Using the SPI ..................................................... 28

Hardware Interface..................................................................... 29

Configuration Without the SPI ................................................ 29

SPI Accessible Features .............................................................. 29

Memory Map .................................................................................. 30

Reading the Memory Map Register Table............................... 30

Memory Map Register Table ..................................................... 31

Memory Map Register Descriptions ........................................ 34

Applications Information .............................................................. 36

Design Guidelines ...................................................................... 36

Power and Ground Recommendations ................................... 36

Clock Stability Considerations ................................................. 36

Exposed Pad Thermal Heat Slug Recommendations ............ 36

VCM ............................................................................................. 36

Reference Decoupling ................................................................ 36

SPI Port ........................................................................................ 36

Outline Dimensions ....................................................................... 37

Ordering Guide .......................................................................... 37

REVISION HISTORY

4/13—Rev. 0 to Rev. A

Changes to Table 1 ............................................................................ 3

Changes to AC Specifications Section ........................................... 4

Added Propagation Delay of 1.5 ns Min and 3.1 ns Max; Table 4 .. 6

Added CLK Divider = 8 to Figure 7, Figure 9, Figure 10, and

Figure 11 Captions.......................................................................... 11

Changes to Figure 14 and Figure 17 ............................................. 12

Added CLK Divider = 8 to Figure 22, Figure 24, and Figure 25

Captions ........................................................................................... 14

Added CLK Divider = 4 to Figure 28 and Figure 31; Changes to

Figure 32 .......................................................................................... 15

Changes to Figure 36 and Figure 37 ............................................. 17

Changes to Figure 56 ...................................................................... 22

Changes to Digital Outputs and Timing Section ....................... 23

Changes to Channel Specific Registers Section .......................... 30

Changes to Register 0x21, Bit 3; Table 17 .................................... 33

Changes to Bits[6:4]—Input Clock Phase Adjust Section......... 35

Added Clock Stability Considerations Section ........................... 36

Updated Outline Dimensions ....................................................... 37

Rev. A | Page 2 of 40

10/11—Revision 0: Initial Version

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