that is designed for low power, wireless applications. It features
a 12-bit analog-to-digital converter (ADC), a low power ARM®
Cortex®-M3 processor, a 862 MHz to 928 MHz and 431 MHz
to 464 MHz RF transceiver, and Flash®/EE memory. The
ADuCRF101
is packaged in a 9 mm × 9 mm LFCSP.
The data acquisition section consists of a 12-bit SAR ADC.
The six inputs can be configured in single-ended or differential
mode. When configured in single-ended mode, they can be
used for ratiometric measurements on sensors that are powered,
when required, from the internal low dropout regulator (LDO).
An internal battery monitor channel and an on-chip tempera-
ture sensor are also available.
This wireless data acquisition system is designed to operate in
battery-powered applications where low power is critical. The
device can be configured in normal operating mode or different
low power modes under direct program control. In flexi mode,
any peripheral can wake up the device and operate it. In hibernate
mode, the internal wake-up timer remains active. In shutdown
mode, only an external interrupt can wake up the device.
The
ADuCRF101
integrates a low power ARM Cortex-M3
processor. It is a 32-bit RISC machine, offering up to 1.25 DMIPS
peak performance. The ARM Cortex-M3 processor also has a
flexible 14-channel direct memory access (DMA) controller that
supports communication peripherals, serial peripheral interface
(SPI), UART, and I
2
C. Also provided on chip are 128 kB of
nonvolatile Flash/EE memory and 16 kB of SRAM.
ADuCRF101
A 16 MHz on-chip oscillator generates the system clock. This
clock can be internally divided for the processor to operate at
a lower frequency, thus saving power. A low power, internal
32 kHz oscillator is available and can be used to clock the four
timers, as follows: two general-purpose timers, a wake-up timer,
and a system watchdog timer.
A range of communication peripherals can be configured, as
required, in a specific application. These peripherals include
UART, I
2
C, SPI, GPIO ports, PWM, and RF transceivers.
The RF transceiver communicates in the 862 MHz to 928 MHz
and 431 MHz to 464 MHz frequency bands using multiple
configurations.
On-chip factory firmware supports in-circuit serial download
via the UART, and nonintrusive emulation and program download
are also supported via the serial wire interface. These features
are incorporated into a low cost development system supporting
this precision analog microcontroller family.
The
ADuCRF101
operates from 2.2 V to 3.6 V and is specified
over an industrial temperature range of −40°C to +85°C. It is
available in a 64-lead LFCSP package.
Rev. A | Page 3 of 19
ADuCRF101
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Data Sheet
AVDD = IOVDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, V
REF
= 1.25 V internal reference, f
CORE
= 16 MHz, T
A
= −40°C to +85°C,
unless otherwise noted. Default ADC sampling frequency of 167 kSPS (eight acquisition clocks and ADC clock frequency of 4 MHz).
Table 1.
Parameter
DC ACCURACY
Resolution
Integral Nonlinearity
Test Conditions/Comments
Single-ended input mode; applies to all ADC
input channels
V
REF
= 1.25 V from internal reference
V
REF
= 1.8 V from LDO
Differential Nonlinearity
DC Code Distribution
Differential
Ratiometric Measurement
CALIBRATED ENDPOINT ERRORS
Offset Error
Gain Error
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Signal-to-Noise + Distortion Ratio
(SINAD)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range
(SFDR)
ANALOG INPUT
Input Voltage Ranges
2
Single-Ended Input
Differential Input
Leakage Current
Input Capacitance
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Accuracy
Reference Temperature Coefficient
Power Supply Rejection Ratio
(PSRR)
Output Impedance
Internal V
REF
Power-On Time
TEMPERATURE SENSOR
2
Voltage Output at 25°C
Voltage Temperature Coefficient
Thermal Impedance
CURRENT CONSUMPTION
Cortex-M3 in Shutdown Mode
Cortex-M3 in Hibernate Mode
RF Transceiver in Sleep Mode
Memory Retained
Memory Not Retained
Rev. A | Page 4 of 19
Min
Typ
Max
Unit
Guaranteed no missing code at 167 kSPS
ADC input shorted, V
CM
= 0.4 V
Using two 10 kΩ resistors
Measured using the factory-set default values of
the ADCOF and ADCGN registers
1
12
−2.5 to
+1
−2.5 to
+0.5
±1
1
5
Bits
LSB
LSB
LSB
LSB
LSB
±1.6
±1
f
IN
= 1 kHz sine wave
68
66
−69
70
LSB
LSB
dB
dB
dB
dB
0
0
Excluding VREF pin
During ADC acquisition
100
20
1.25
±5
±40
60
2
5
435
1.14
35
RF transceiver in sleep mode, memory not retained
Wake-up timer running from external 32 kHz
crystal, 8 kB of SRAM retained (8 kB not retained)
280
V
REF
V
CM
± V
REF
/2
V
V
nA
pF
V
mV
ppm/°C
dB
Ω
ms
mV
mV/°C
°C/W
nA
Measured at T
A
= 25°C
0.47 µF external capacitor
Indicates die temperature
1.9
1.75
µA
µA
Data Sheet
Parameter
RF Transceiver in Receive Mode
RF Transceiver in Transmit Mode
Cortex-M3 in Active Mode
Static Current
Dynamic Current
START-UP TIME
2
From Flexi Mode
From Hibernate Mode
From Power-On and Shutdown
Mode
RF Link, Waking Up from Sleep
Mode
POWER SUPPLY REQUIREMENTS
Power Supply Voltage Range
2
POWER SUPPLY MONITOR
Trip Point Voltage
WATCHDOG TIMER
2
Timeout Period
FLASH/EE MEMORY
2
Endurance
3
Data Retention
4
DIGITAL INPUTS
Input Current (Leakage Current)
Input Capacitance
LOGIC INPUTS
Input Low Voltage, V
INL
Input High Voltage, V
INH
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
32.768 kHz CRYSTAL
Input Current (Leakage Current)
LFXTAL1 Input Capacitance
LFXTAL2 Output Capacitance
26 MHz CRYSTAL
XOSC26P Input Capacitance
XOSC26N Output Capacitance
INTERNAL HIGH FREQUENCY (HF)
OSCILLATOR
Tolerance
INTERNAL LOW FREQUENCY (LF)
OSCILLATOR
Tolerance
MCU CLOCK DIVIDER
2
EXTERNAL CLOCK INPUT
2
Range
1
2
ADuCRF101
Test Conditions/Comments
Min
Typ
12.8
9 to 32
Max
Unit
mA
mA
RF transceiver idle (PHY_ON state or PHY_OFF
state)
1
2.0
210
FCLK is the Cortex-M3 clock or divided version of
the 16 MHz oscillator
From wake-up event to user code execution
From applying power/asserting active external
interrupt to user code execution
Includes 310 µs for 26 MHz crystal startup
(7 pF load capacitor at T
A
= 25°C)
2.2
2
Programmable
0
10,000
10
10
10
512
3 to 5
13.4
55
562.8
mA
µA/MHz
FCLK
µs
ms
µs
3.6
V
V
sec
Cycles
Years
nA
pF
T
J
= 85°C
All digital inputs, excluding LFXTAL1 and XOSC26P
V
INH
= IOVDD or V
INH
= 2.2 V, pull-up disabled;
V
INL
= 0 V, pull-up disabled
Excluding P2.4
All logic inputs, including LFXTAL1 but excluding
XOSC26P
0.2 × IOVDD
0.7 × IOVDD
I
SOURCE
= 1 mA
I
SINK
= 1 mA
32.768 kHz crystal, for use with timers
V
INH
= IOVDD or V
INH
= 2.2 V, V
INL
= 0 V
IOVDD − 0.4
0.36
50
5
5
10
10
16
±3
32.768
±20
Eight programmable core clock dividers
External MCU clock range allowed
1
32.768
128
16,000
V
V
V
V
nA
pF
pF
pF
pF
MHz
%
kHz
%
Processor clock by default
kHz
For detailed information, see the
UG-231 User Guide.
These values are not production tested; they are guaranteed by design and/or characterization data at production release.
3
Endurance is qualified to 10,000 cycles as per JEDEC Standard No. 22-A117 and measured at −40°C, +25°C, and +85°C. Typical endurance at 25°C is 170,000 cycles.
4
Retention lifetime equivalent at a junction temperature (T
J
) of 85°C as per JEDEC Standard No. 22-A117. Retention lifetime derates with junction temperature.
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