NCP1612GEVB
160-W, Wide Mains, PFC
Stage Driven by the
NCP1612 Evaluation Board
User's Manual
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EVAL BOARD USER’S MANUAL
Introduction
Housed in a SO-10 package, The NCP1612 is designed to
drive PFC boost stages in so-called Current Controlled
Frequency Fold-back (CCFF). In this mode, the circuit
classically operates in Critical conduction Mode (CrM)
when the inductor current exceeds a programmable value.
When the current is below this preset level, the NCP1612
linearly decays the frequency down to about 20 kHz when
the current is nearly zero. CCFF maximizes the efficiency
throughout the load range. Incorporating protection features
for rugged operation, it is furthermore ideal in systems
where cost-effectiveness, reliability, low stand-by power
and high-efficiency are the key requirements.
Extremely slim, the NCP1612 evaluation board is
designed to be less than 13-mm high. This low-profile PFC
Table 1. ELECTRICAL SPECIFICATIONS
Description
Input Voltage Range
Line Frequency Range
Output Power
Minimum Output Load Current(s)
Number of Outputs
Nominal Output Voltage
Maximum Startup Time
Target Efficiency at Full Load (115 V
rms
)
Load Conditions For Efficiency Measurements (10%, 20%,..)
Minimum Efficiency At 20% Load, 115 V
rms
Minimum PF Over The Line Range At Full Load
Hold-Up Time (the output voltage remaining above 300 V)
Peak To Peak Low Frequency Output Ripple
stage is intended to deliver 160 W under a 390 V output
voltage from a wide mains input. This is a PFC boost
converter as used in Flat TVs, High Power LED Street Light
power supplies, and all-in-one computer supplies. The demo
board embeds the NCP1612 B-version which is best
appropriate for the self-biased configuration. The board is
also configurable to have the NCP1612 powered from an
external power source. In this case, apply a V
CC
voltage that
exceeds the NCP1612B start-up level (18.2 V max) to
ensure the circuit start of operation or solder the NCP1612A
instead. The low V
CC
start-up level of the A-version
(11.25 V max.) allows the circuit powering from a 12-V rail.
Both versions feature a large V
CC
operating range (from
9.5 V up to 35 V).
Value
90-265
45 to 66
160
0
1
390
<3
95
10-100
93
95
> 10
<8
Units
Vrms
Hz
W
Adc
Vdc
s
%
%
%
%
ms
%
©
Semiconductor Components Industries, LLC, 2012
April, 2012
−
Rev. 1
1
Publication Order Number:
EVBUM2051/D
NCP1612GEVB
THE BOARD
Figure 1. A Slim Board (Height < 13 mm)
APPLICATION SCHEMATIC
Vin
U1
GBU606
L2
200
μH
(np/ns=10)
+
C4
220nF
Type = X2
IN
C5
470 nF / 400 V
−
.
.
D2
1N5406
D1
MUR550
Rth1
B57153S150M
Vaux
R2
1000k
R1
1000k
C1
1 nF
Type = Y2
V line
R6
22
D3
1N4148
DRV
R5
2.2
Q1
IPA50R250
Vbulk
CM1
C2
1 nF
Type = Y2
Q2
MMBT589LT1G
R4
10k
I sense
R3
80m 3W
L1
150mH
C3
680nF
Type = X2
F1
D4
1N4148
C7
22μF/50V
DZ2
33V
C6a
68μF/450V
C6b
68μF/450V
GND
V CC
+
L
N
Earth
90−265 Vrms
Socket for
External VCC
Power Source
Figure 2. Application Schematic
−
Power Section
If an external V
CC
voltage is applied to the board (as
allowed by the socket for external V
CC
power sourcing),
it should be noted that the NCP1612 latches off if this
voltage exceeds about 30 V (see pfcOK section). In this
−
case, unplug the PFC stage to recover operation. In all
events, do not apply more than 33 V to the V
CC
socket not
to exceed the DZ
2
reverse ZENER voltage (see Figure 2).
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NCP1612GEVB
V line
Vbulk
R8
560k
R22
560k
R9
1800k
R23
1800k
R11
27k
C8
1nF
R10
1800k
R30
27k
C17
1nF
R29
1800k
R28
1800k
R27
560k
R17
120k
R16
120k
R15
120k
V in
BUV
V CC
R32
120k
D6
1N4148
C13
10nF
R18
27
D5
1N4148
R24
1800k
pfcOK
1
2
10
9
8
7
6
V aux
R20
4.7k
R25
1800k
3
4
R7
0
DRV
R21
4.7k
R12
27k
R26
120k
C10
220nF
5
I sense
C16
470pF
C9
2.2μF
R14
270k
C11
220nF
R13
120k
C18
10nF
R33
39k
C15
220nF
DZ1
22V
GND
Figure 3. Application Schematic
−
Control Section
GENERAL BEHAVIOR
−
TYPICAL WAVEFORMS
V
BULK
Line current (2 A/div)
V
BULK
V
IN
Line current (2 A/div)
V
IN
Voltage on FF
CONTROL
pin
Voltage on FF
CONTROL
pin
a.) 115 V
b.) 230 V
Figure 4. General Waveforms at Full Load
CCFF OPERATION
The NCP1612 operates in so called Current Controlled
Frequency Fold-back (CCFF) where the circuit operates in
Critical conduction Mode (CrM) when the instantaneous
line current is medium or high. When this current is lower
than a preset level, the frequency linearly decays to about
20 kHz. CCFF maximizes the efficiency at both nominal
and light loads (*). In particular, stand-by losses are
minimized.
To further optimize the efficiency, the circuit skips cycles
near the line zero crossing where the power transfer is
particularly inefficient. This is at the cost of some current
distortion. If superior power factor is needed, forcing a
minimum 0.75 V voltage on the “FFcontrol” inhibits this
function.
Practically, the FFcontrol pin of the NCP1612 generates
a voltage representative of the instantaneous line current.
When this voltage exceeds 2.5 V, the circuit operates in CrM.
If the FFcontrol voltage is below 2.5 V, the circuit forces a
delay (or dead-time) before re-starting a DRV cycle which
is proportional to the difference between 2.5 V reference and
the FFcontrol voltage. This delay is maximum when the
FFcontrol voltage is 0.75 V (about 45
ms)
so that a nearly
20 kHz operation is obtained. Below this 0.75 V level, the
circuit skips cycles.
*Like in FCCrM controllers, internal circuitry allows near-unity power factor even when the switching frequency is reduced.
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NCP1612GEVB
Line current
Voltage on FF
CONTROL
pin
Line current
DRV
DRV
Voltage on FF
CONTROL
pin
V
DS
V
DS
a) CrM operation at the top of the sinusoid
Line current
DRV
b) Reduced frequency at a lower level of the sinusoid
Voltage on FF
CONTROL
pin
V
DS
c) Low frequency near the line zero crossing
Figure 5. CCFF Operation (230 V, 0.2 A Load Current)
Figure 5 illustrates the CCFF operation at 230 V, 200 mA
loading the PFC stage:
1. At the top of the sinusoid, the FFcontrol pin
voltage (that is representative of the line current)
exceeds 2.5 V and the circuit operates in critical
conduction mode (see Figure 5a).
2. As the input voltage decays, so do the line current
and the FFcontrol pin voltage. The FFcontrol
being lower than 2.5 V, the circuit starts to reduce
the frequency. (see Figure 5b).
3. Near the zero crossing the frequency is further
decreased (see Figure 5c).
In all cases, the circuit turns on at a valley:
•
At the first valley as classically done in CrM operation
•
Or at the first valley following the completion of the
dead-time generated by the CCFF function to reduce
the frequency.
•
The circuit nicely stays “locked” on to valley n until it
needs to jump to either valley (n-1) or valley (n+1). In
other words, there is no inappropriate transition
between two valleys
One can also note that the switching frequency being less
when the line current is low, the frequency is particularly
low at light load, high line, CrM operation being more likely
to occur at heavy load, low line. Experience shows that this
behavior helps optimize the efficiency in all conditions.
Similarly, the skipping period of time (near the line zero
crossing) visible in Figure 9 (for the particular case of the
operation at 265 V and 20% of the load):
•
Is nonexistent or very short at low line, heavy load
•
Is longer when the load diminishes and the line
magnitude
Let us remind that the skip function optimizes the
efficiency but this is at the cost of a limited current
distortion. If superior power factor is needed, forcing a
minimum 0.75 V voltage on the “FFcontrol” pin inhibits this
function.
Refer to the data sheet for a detailed explanation of the
CCFF operation and of its implementation in the NCP1612
[3].
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NCP1612GEVB
Line current
V
IN
DRV
Voltage on FF
CONTROL
pin
DRV
Line current
V
IN
Voltage on FF
CONTROL
pin
a) Soft Skip Beginning
b) Soft Operation Recovery
Figure 6. The NCP1612 Enters and Leaves Skip Mode in a Soft Manner
As illustrated by Figure 6, the circuit does not abruptly
interrupt the switching when it enters skip mode. Instead, the
on-time is gradually decreased to zero in 3 to 4 switching
periods typically. Similarly, the circuit recovers operation in
a soft manner.
NO LOAD LOSSES
The input power is measured no load being connected. An external 15-V V
CC
is applied.
Resistors R
15
, R
16
and R
17
of Figure 3 that are implemented to charge the V
CC
capacitor at start-up, draw a large bias current
V
in
*
V
cc
from the input voltage. They are disconnected for this test.
R
15
)
R
16
)
R
17
In these conditions, we measured:
115 V (60 Hz)
Input power
I
CC
92 mW
2.0 mA
230 V (50 Hz)
118 mW
1.9 mA
The V
CC
consumption is almost constant over the V
CC
range (e.g., 2.2 mA at 30 V, low line).
It must be noted that the input power mainly results from static losses:
•
Discharge resistors for X2 capacitors (R
1
and R
2
of Figure 2) consume
V
line,rms
R
1
)R
2
2
that is about 7 mW at 115 V and
26 mW at 230 V.
•
Two resistors sensing networks are implemented to sense the bulk voltage (redundant bulk voltage monitoring). At both
line voltages, they consume
V
bulk
V
bulk
)
R
8
)R
9
)R
10
)R
11
R
22
)R
23
)R
24
)R
25
2
2
that is about 72 mW. These losses can be
easily reduced if needed by using one single resistors divider for pins 1 and 2 and/or by increasing the impedance of the
sensing networks.
These static losses cost 79 mW at low line and 98 mW at
high line. As a matter of fact, the losses linked to the PFC
stage operation are very small.
The measurements were made at 25°C ambient
temperature by means of a power meter CHROMA 66202
used in accumulation mode (W.h measurement over
6 minutes, the result being multiplied by 10 to obtain the
averaged power).
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