DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
Page 1 of 3
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DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
Overview
DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over
75MHz. DDR SDRAM is similar in function to the regular SDRAM but doubles the bandwidth of the memory by
transferring data twice per cycle on both edges of the clock signal, implementing burst mode data transfer.
The DDR SDRAM Controller is a parameterized core giving user the flexibility for modifying the data widths, burst
transfer rates, and CAS latency settings of the design. In addition, the DDR core supports intelligent bank
management, which is done by maintaining a database of "all banks activated" and the "rows activated" in each bank.
With this information, the DDR SDRAM Controller decides if an active or pre-charge command is needed. This
effectively reduces the latency of read/write commands issued to the DDR SDRAM.
Features
Performance of Greater than 100MHz (200 DDR)
Interfaces to JEDEC Standard DDR SDRAMs
Supports DDR SDRAM Data Widths of 16, 32 and 64 Bits
Supports up to 8 External Memory Banks
Programmable Burst Lengths of 2, 4, or 8
Programmable CAS Latency of 1.5, 2.0, 2.5 or 3.0
Byte-level Writing Supported
Increased Throughput Using Command Pipelining and Bank Management
Supports Power-down and Self Refresh Modes
Automatic Initialization
Automatic Refresh During Nomal and Power-down Modes
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10/10/2011
DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
Page 2 of 3
Timing and Settings Parameters Implemented as Programmable Registers
Bus Interfaces to PCI Target, PowerPC and AMBA (AHB) Buses Available
Complete Synchronous Implementation
Evaluation Configurations
Performance and Resource Utilization for ORCA 4
Parameter File
Core Configuration
ORCA 4 PFUs
LUTs
Registers
Dist. RAM
3
fMAX (MHz)
External Pins
SysMEM
TM
2
1
ddrct_gen_o4_1_008.lpc ddrct_ahb_o4_1_008.lpc
Generic I/F
344
1359
1559
N/A
100 (200 DDR)
239
N/A
AHB I/F
560
2322
2451
18
100 (200 DDR)
242
N/A
EBRs
Parameter File
Core Configuration
ORCA 4 PFUs
LUTs
Registers
Dist. RAM
3
fMAX (MHz)
External Pins
SysMEM
TM
2
ddrct_pci_o4_1_008.lpc ddrct_ppc_o4_1_008.lpc
PCI I/F
510
2024
2070
16
66
4
PPC I/F
492
1922
2170
18
100 (200 DDR)
181
N/A
246
N/A
EBRs
Performance and utilization characteristics are generated using an OR4E022BA352 in ispLEVER
TM
v.3.0 software
except for the AHB configuration 008 which is generated using OR4E042BM416. Synthesized using Synplicity Synplify,
v.7.0.3. When using this IP core in a different density, package, speed, or grade within the ORCA Series 4 family,
performance may vary slightly.
2
3
4
1
PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.
Dist. RAM = distributed memory.
Performance for the PCI configuration of this DDR core is limited by the maximum throughput of the PCI 2.2 interface
(66MHz).
All parameters are set to their default values as shown in the Data Sheet.
5
Performance and Resource Utilization for XPGA
1
Parameter File
Device
Core Configuration
ddrct_gen_xp_1_002.lpc ddrct_ahb_xp_1_002.lpc
LFX125B-4FH516CES/2X LFX500B-4FH516CES/2X
Generic I/F
AHB I/F
http://www.latticesemi.com/products/intellectualproperty/ipcores/ddrsdramcontroller.cfm
10/10/2011
DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
Page 3 of 3
ispXPGA PFUs
2
LUTs
Registers
f
MAX
External Pins
SysMEM
TM
393
1116
910
100
142
N/A
751
1928
1599
100
145
N/A
EBRs
Parameter File
Device
Core Configuration
ispXPGA PFUs
2
LUTs
Registers
f
MAX
External Pins
SysMEM
TM
EBRs
ddrct_pci_xp_1_002.lpc ddrct_ppc_xp_1_002.lpc
LFX500C-4FH516CES/2X LFX500B-4FH516CES/2X
PCI I/F
688
1867
1333
66
3
PPC I/F
647
1670
1392
100
154
N/A
170
N/A
1
Performance and utilization characteristics are generated using the ispXPGA device shown above in ispLEVER v.3.1
2
software. The evaluation version of this IP core only works on this specific device density, package and speed grade.
PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.
3
Performance for the PCI configuration of this DDR core is limited by the maximum throughput of the PCI 2.2 interface
(66MHz).
Ordering Information
Part Numbers:
For ORCA 4:
DDRCT-GEN-O4-N1
DDRCT-PPC-O4-N1
DDRCT-PCI-O4-N1
DDRCT-AHB-O4-N1
For ispXPGA:
DDRCT-GEN-XP-N1
DDRCT-PCI-XP-N1
DDRCT-AHB-XP-N1
DDRCT-PPC-XP-N1
To find out how to purchase the DDR SDRAM Controller - Pipelined IP Core, please contact your
local Lattice Sales
Office.
http://www.latticesemi.com/products/intellectualproperty/ipcores/ddrsdramcontroller.cfm
10/10/2011
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