Features
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Low Current Consumption: I
DD
< 100 µA
RC Oscillator
Internal Reset During Power-up and Supply Voltage Drops (POR)
“Short” Trigger Window for Active Mode
“Long” Trigger Window for Sleep Mode
Cyclical Wake-up of the Microcontroller in Sleep Mode
Trigger Input
Six Wake-up Inputs
Reset Output
Enable Output
Digital Window
Watchdog Timer
U5020M
Description
The digital window watchdog timer, U5020M, is a CMOS integrated circuit. In applica-
tions where safety is critical, it is especially important to monitor the microcontroller.
Normal microcontroller operation is indicated by a cyclically transmitted trigger signal,
which is received by a window watchdog timer within a defined time window.
A missing or a wrong trigger signal causes the watchdog timer to reset the microcon-
troller. The IC is tailored for microcontrollers which can work in both full-power and
sleep mode. With an additional voltage monitoring (power-on reset and supply voltage
drop reset), the U5020M offers a complete monitoring solution for microsystems in
automotive and industrial applications.
Rev. 4755A–AUTO–11/03
Figure 1.
Block Diagram with External Ciruit
C
V
DD
OSC
C
1
Reset
Input t
s
10
15
10 nF
13
RC
Oscillator
OSC
R
1
V
DD
Micro-
controller
16
OSC
State machine
9
Enable
Power-on
reset
POR
Test logic
External
switching
circuitry
Trigger
11
Input signal
conditioning
POR
Mode 12
Wake up 3-8
14
GND
2
Test
1
Test
Pin Configuration
Figure 2.
Pinning SO16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TS
OSC
GND
VDD
MODE
TRIG
RESET
ENA
TM
TM
WAKE-UP
WAKE-UP
WAKE-UP
WAKE-UP
WAKE-UP
WAKE-UP
2
U5020M
4755A–AUTO–11/03
U5020M
Pin Description
Pin
1
2
3 to 8
Symbol
TM
TM
WAKE-UP
Function
Test must not be connected
Test must be connected to GND
Wake-up inputs (pull-down resistor)
There are six digitally debounced wake-up inputs. During the long trigger mode each signal slope at the
inputs initiates a reset pulse at pin 10.
Enable output (push-pull)
It is used for the control of peripheral components. It is activated after the processor triggers three times
correctly.
Reset output (open drain)
Resets the processor in the case of a trigger error or if a wake-up pulse occurs during the long watchdog
period.
Trigger input (pull-up resistor)
It is connected to the microprocessor’s trigger signal.
Mode input (pull-up resistor)
The processor’s mode signal initiates the switchover between the long and the short watchdog time.
Supply voltage
Ground, reference voltage
RC oscillator
Time switch input
Programming pin to select different time durations for the long watchdog time.
9
ENA
10
RESET
11
12
13
14
15
16
TRIG
MODE
VDD
GND
OSC
TS
Functional
Description
Supply, Pin 13
The U5020M requires a stabilized supply voltage V
DD
= 5 V ±5% to comply with its elec-
trical characteristics.
An external buffer capacitor of C = 10 nF may be connected between pin 13 and GND.
RC Oscillator, Pin 15
The clock frequency, f, can be adjusted by the components R
1
and C
1
according to the
formula:
1
f
= --
-
t
where t = 1.35 + 1.57 R
1
(C
1
+ 0.01)
R
1
in k
W
, C
1
in nF and t in µs
The clock frequency determines all time periods of the logic part as shown in the table
“Electrical Characteristics” under the subheading “Timing” on page 8. With an appropri-
ate component selection, the clock frequency, f, is nearly independent of the supply
voltage as shown in Figure 3 on page 4.
Frequency tolerance
D
f
max
= 10% with R
1
±1%, C1 = ±5%
3
4755A–AUTO–11/03
Figure 3.
Period t versus R
1
, at C
1
= 500 pF
1000.00
100.00
t (µs)
4.5 V
10.00
5.0 V
5.5 V
C
1
= 500 pF
1.00
1
10
100
1000
R
1
(kΩ)
Figure 4.
Power-up Reset and Mode Switchover
Pin 13
V
DD
t
0
t
6
Pin 10
Reset out
t
1
Mode
Pin 12
Supply Voltage
Monitoring, Pin 10
The integrated power-on reset (POR) circuitry sets the internal logic to a defined basic
status and generates a reset pulse at the reset output, pin 10, during ramp-up of the
supply voltage and in the case of voltage drops of the supply. A hysteresis in the POR
threshold prevents the circuit from oscillating. During ramp-up of the supply voltage, the
reset output stays active for a specified period of time (t
0
) in order to bring the microcon-
troller in its defined reset status (see Figure 4). Pin 10 has an open-drain output.
The switch-over mode time enables the synchronous operation of microcontroller and
watchdog. When the power-up reset time has elapsed, the watchdog has to be switched
to monitoring mode by the microcontroller by a “low” signal transmitted to the mode pin
(pin 12) within the time-out period, t
1
. If the low signal does not occur within t
1
, (see Fig-
ure 4) the watchdog generates a reset pulse, t
6
, and the time, t
1
, starts again.
Microcontroller and watchdog are synchronized with the switchover mode time, t
1
, each
time a reset pulse is generated.
Switch-over Mode Time,
Pin 12
4
U5020M
4755A–AUTO–11/03
U5020M
Microcontroller in Active Mode
Monitoring with the “Short”
Trigger Window
After the switch-over mode the watchdog operates in short watchdog mode and expects
a trigger pulse from the microcontroller within the defined time window, t
3
, (enable time).
The watchdog generates a reset pulse which resets the microcontroller if
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the trigger pulse duration is too long
the trigger pulse is within the disable time, t
2
there is no trigger pulse
Figure 5 shows the pulse diagram with a missing trigger pulse.
Figure 5.
Pulse Diagram with no Trigger Pulse During the Short Watchdog Time
V
DD
Pin 13
t
0
t
1
Pin 10
Reset out
t
2
Mode
t
3
Pin 12
Pin 11
Trigger
Figure 6 on page 6 shows a correct trigger sequence. The positive edge of the trigger
signal starts a new monitoring cycle with the disable time, t
2
. To ensure correct opera-
tion of the microcontroller, the watchdog needs to be triggered three times correctly
before it sets its enable output. This feature is used to activate or deactivate safety-criti-
cal components which have to be switched to a certain condition (emergency status) in
the case of a microcontroller malfunction. As soon as there is an incorrect trigger
sequence, the enable signal is reset and it takes a sequence of three correct triggers
before enable is reset.
Microcontroller in Sleep Mode
Monitoring with the “Long”
Trigger Window
The long watchdog mode allows cyclical wake-up of the microcontroller during sleep
mode. As in short watchdog mode, there is a disable time, t
4
, and an enable time, t
5
, in
which a trigger signal is accepted. The watchdog can be switched from the short trigger
window to the long trigger window with a “high” potential at the mode pin (pin 12). In
contrast to the short watchdog mode, the time periods are now much longer and the
enable output remains inactive so that other components can be switched off to effect a
further decrease in current consumption. As soon as a wake-up signal at one of the 6
wake up inputs (pins 3 to 8) is detected, the long watchdog mode ends, a reset pulse
wakes-up the sleeping microcontroller and the normal monitoring cycle starts with the
mode switch-over time.
By means of a low or high potential at pin 16 (time switch), two values for the long
watchdog time can be selected.
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4755A–AUTO–11/03
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