IP-SDI-II datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Development board/suite/development tools> IP-SDI-II

IP-SDI-II: DescriptionDevelopment Software SDI II Video MegaCore; CategoryDevelopment board/suite/development tools; File Size644KB，85 Pages; ManufacturerAltera (Intel)

Download Datasheet Parametric View All

IP-SDI-II Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	IP-SDI-II	-	-	View	Buy Now

IP-SDI-II Overview

Development Software SDI II Video MegaCore

IP-SDI-II Parametric

Parameter Name	Attribute value
Product Category	Development Software
Manufacturer	Altera (Intel)
RoHS	Not Applicableduscyacyzqfqybrreqfd
Product	Software Developer Kits
For Use With	Arria V, Stratix V
Description/Function	SDI II MegaCore Function
Factory Pack Quantity	1

Preview

Download Datasheet

View All

Intel

FPGA SDI II IP Core User

Guide

Updated for Intel

Quartus

Prime Design Suite:

17.1

Send Feedback

UG-01125 | 2017.11.06

Latest document on the web:

PDF

HTML

Contents

1 Intel

FPGA SDI II IP Core Quick Reference.................................................................... 4

2 Intel FPGA SDI II IP Core Overview.................................................................................6

2.1 General Description................................................................................................ 7

2.2 Performance and Resource Utilization........................................................................ 7

3 Intel FPGA SDI II IP Core Getting Started..................................................................... 10

3.1 Installing and Licensing Intel FPGA IP Cores............................................................. 10

3.1.1 Intel FPGA IP Evaluation Mode.................................................................... 10

3.2 Design Walkthrough.............................................................................................. 13

3.2.1 Creating a New Intel Quartus Prime Project.................................................. 13

3.2.2 Launching IP Catalog.................................................................................14

3.2.3 Parameterizing the IP Core.........................................................................14

3.2.4 Generating a Design Example and Simulation Testbench.................................15

3.3 Intel FPGA SDI II IP Core Component Files...............................................................15

3.4 Compiling the Intel FPGA SDI II IP Core Design........................................................ 15

3.5 Programming an FPGA...........................................................................................16

4 Intel FPGA SDI II IP Core Parameters........................................................................... 17

5 Intel FPGA SDI II IP Core Functional Description.......................................................... 19

5.1 Protocol...............................................................................................................20

5.1.1 Transmitter.............................................................................................. 20

5.1.2 Receiver.................................................................................................. 23

5.2 Transceiver.......................................................................................................... 27

5.3 Submodules......................................................................................................... 28

5.3.1 Insert Line............................................................................................... 28

5.3.2 Insert/Check CRC..................................................................................... 29

5.3.3 Insert Payload ID...................................................................................... 29

5.3.4 Match TRS............................................................................................... 31

5.3.5 Scrambler................................................................................................ 31

5.3.6 TX Sample............................................................................................... 31

5.3.7 Clock Enable Generator..............................................................................31

5.3.8 RX Sample............................................................................................... 32

5.3.9 Detect Video Standard...............................................................................32

5.3.10 Detect 1 and 1/1.001 Rates...................................................................... 33

5.3.11 Transceiver Controller.............................................................................. 33

5.3.12 Descrambler........................................................................................... 33

5.3.13 TRS Aligner............................................................................................ 33

5.3.14 3Gb Demux............................................................................................ 34

5.3.15 Extract Line............................................................................................ 34

5.3.16 Extract Payload ID...................................................................................34

5.3.17 Detect Format.........................................................................................35

5.3.18 Sync Streams......................................................................................... 35

5.3.19 Convert SD Bits...................................................................................... 35

5.3.20 Insert Sync Bits...................................................................................... 36

5.3.21 Remove Sync Bits................................................................................... 37

5.4 Optional Features..................................................................................................37

Intel

FPGA SDI II IP Core User Guide

Contents

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

HD-SDI Dual Link to 3G-SDI (Level B) Conversion......................................... 37

3G-SDI (Level B) to HD-SDI Dual Link Conversion......................................... 38

SMPTE RP168 Switching Support.................................................................39

SD 20-Bit Interface for Dual/Triple Rate....................................................... 40

Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices......... 40

6 Intel FPGA SDI II IP Core Signals.................................................................................. 43

6.1 Intel FPGA SDI II Core Resets and Clocks.................................................................43

6.2 Transmitter Protocol Signals................................................................................... 48

6.2.1 Image Mapping ........................................................................................51

6.3 Receiver Protocol Signals....................................................................................... 52

6.3.1 rx_format................................................................................................ 57

6.4 Transceiver Signals .............................................................................................. 58

7 Intel FPGA SDI II IP Core Design Considerations.......................................................... 61

7.1 Transceiver Handling Guidelines.............................................................................. 61

7.1.1 Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices..................... 61

7.1.2 Handling Transceiver in Intel Arria 10 and Intel Stratix 10 Devices...................64

7.2 Timing Violation....................................................................................................68

8 Design Example for Arria V, Cyclone V, and Stratix V Devices........................................ 69

8.1 Design Example Components................................................................................. 72

8.1.1 Video Pattern Generator.............................................................................73

8.1.2 Transceiver Reconfiguration Controller......................................................... 73

8.1.3 Reconfiguration Management......................................................................74

8.1.4 Reconfiguration Router.............................................................................. 75

8.1.5 Avalon-MM Translators...............................................................................75

8.2 Design Reference..................................................................................................76

8.2.1 Video Pattern Generator Signals..................................................................76

8.2.2 Transceiver Reconfiguration Controller Signals.............................................. 77

8.2.3 Reconfiguration Management Parameters.................................................... 78

8.2.4 Reconfiguration Router Signals................................................................... 79

8.3 Simulating the Intel FPGA SDI II IP Core Design....................................................... 79

8.3.1 Simulation Run Time................................................................................. 80

A Intel FPGA SDI II IP Core User Guide Archives.............................................................. 81

B Revision History for Intel FPGA SDI II IP Core User Guide............................................ 82

Intel

FPGA SDI II IP Core User Guide

Recommended Resources

Chandelier brightness controller circuit 2

Wireless headphone circuit

Low power consumption timing circuit

Pulsed infrared LED driver circuit diagram

Limit control circuit diagram

Photoelectric ignition circuit

Received the X-NUCLEO-IKS01A3 sensor kit: I received the text message yesterday evening and immediately went to the collection point to pick up the express delivery after dinner. I opened the outer package and revealed the sensor kit (see the...; hujj ST Sensors & Low Power Wireless Technology Forum

sbc9261 control board, at91sam9261, high speed 240mhz, direct naked, provide full code: Features u Directly running (Linux and Windows CE operating systems are optional) u On-board integrated 64MB SDRAM, 256MB NandFlash (not soldered by default), 4-16MB NorFlash u 2 USB Host ports and 1 ...; szembed Buy&Sell

HardFault_Handler exception: [table=98%] [tr][td]I would like to ask you, I recently used MDK5.11 to write a program for STM32F103RC, but it inexplicably entered the HardFault_Handler abnormal interrupt. Now I am completely confu...; shipeng stm32/stm8

How did you first learn hardware design?: I am a newbie and haven't gotten started yet. Now I want to learn hardware, but I don't know where to start and what courses I should take. I hope you can give me some advice....; you168you Embedded System

FPGA reads and writes off-chip SDRAM: I want to know if I can write Verilog code to control the SDRAM controller in qsys to read and write SDRAM? If so, what are the methods?...; 全部都是泡馍 FPGA/CPLD

[Power amplifier case] Application of high voltage amplifier in pulse magnetic field analysis of energized air-core coil: [Power amplifier case] Application of high voltage amplifier in pulse magnetic field analysis of energized air-core coil...; aigtekatdz Integrated technical exchanges

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components