About The Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
Contents
About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core..
1-1
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features................... 1-3
Low Latency 40-100GbE IP Core Device Family and Speed Grade Support...................................... 1-4
Device Family Support.................................................................................................................... 1-4
Low Latency 40-100GbE IP Core Device Speed Grade Support............................................... 1-5
IP Core Verification.....................................................................................................................................1-6
Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices...................................... 2-2
Licensing IP Cores....................................................................................................................................... 2-3
OpenCore Plus IP Evaluation........................................................................................................ 2-3
Specifying the Low Latency 40-100GbE IP Core Parameters and Options.........................................2-4
IP Core Parameters......................................................................................................................................2-5
Files Generated for Stratix V Variations.................................................................................................2-14
Files Generated for Arria 10 Variations..................................................................................................2-15
Integrating Your IP Core in Your Design.............................................................................................. 2-18
External Transceiver Reconfiguration Controller Required in Stratix V Designs............... 2-19
Transceiver PLL Required in Arria 10 Designs......................................................................... 2-20
External Time-of-Day Module for Variations with 1588 PTP Feature..................................2-22
Clock Requirements for 40GBASE-KR4 Variations.................................................................2-23
External TX MAC PLL..................................................................................................................2-23
Placement Settings for the Low Latency 40-100GbE IP Core................................................. 2-23
Low Latency 40-100GbE IP Core Testbenches......................................................................................2-23
Low Latency 40-100GbE IP Core Testbench Overview........................................................... 2-24
Understanding the Testbench Behavior..................................................................................... 2-27
Simulating the Low Latency 40-100GbE IP Core With the Testbenches.......................................... 2-28
Generating the Low Latency 40-100GbE Testbench................................................................ 2-29
Optimizing the Low Latency 40-100GbE IP Core Simulation With the Testbenches......... 2-30
Simulating with the Modelsim Simulator...................................................................................2-30
Simulating with the NCSim Simulator....................................................................................... 2-31
Simulating with the VCS Simulator............................................................................................ 2-31
Testbench Output Example: Low Latency 40-100GbE IP Core.............................................. 2-31
Altera Corporation
About The Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
TOC-3
Compiling the Full Design and Programming the FPGA....................................................................2-32
Initializing the IP Core..............................................................................................................................2-32
How to Contact Altera............................................................................................................................. C-11
Low Latency 40- and 100-Gbps Ethernet (40GbE and 100GbE) media access controller
(MAC) and PHY MegaCore
®
functions offer the lowest round-trip latency and smallest size to implement
the
IEEE 802.3ba 40G and 100G Ethernet Standard
with an option to support the
IEEE 802.3ap-2007
Backplane Ethernet Standard.
The version of this product that supports Arria
®
10 devices is included in the Altera MegaCore IP Library
and available from the Quartus
®
Prime IP Catalog.
Note:
The full product name, Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore
Function, is shortened to Low Latency (LL) 40-100GbE IP core in this document. In addition,
although multiple variations are available from the parameter editor, this document refers to this
product as a single IP core, because all variations are configurable from the same parameter editor.
Figure 1-1: Low Latency 40GbE and 100GbE MAC and PHY IP Cores
Main blocks, internal connections, and external block requirements.
PLL (Arria 10 only)
Low Latency 40- or 100-Gbps Ethernet MAC and PHY IP Core
Custom Streaming
Avalon-ST
From
client application logic
Low Latency 40- or 100-GbE
MAC
TX
TX
FIFO
Adapter
TX
MAC
TX
PCS
PHY
To optical module, backplane,
or separate device
Links are:
PMA
XLAUI: 4 x 10.3125 Gbps or
CAUI: 10 x 10.3125 Gbps or
CAUI-4: 4 x 25.78125 Gbps
To
client application logic
Avalon-ST
Custom Streaming
RX
Adapter
RX
MAC
RX
PCS
PMA
From optical module, backplane,
or separate device
Avalon-MM
Control and
Status Interface
Avalon-MM
Arria 10
Transceiver
Reconfiguration
Interface
(Arria 10 only)
Reconfiguration
Controller (Stratix V only)
Avalon-MM
2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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