NB3M8T3910GMNR2G datasheet, PDF

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NB3M8T3910GMNR2G: DescriptionClock u0026 Timer Development Tools NB3M8T3910G Custom EVB; CategoryThe embedded processor and controller Microcontrollers and processors; File Size186KB，20 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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NB3M8T3910GMNR2G Overview

Clock u0026 Timer Development Tools NB3M8T3910G Custom EVB

NB3M8T3910GMNR2G Parametric

Parameter Name	Attribute value
Brand Name	ON Semiconductor
Is it lead-free?	Lead free
Maker	ON Semiconductor
package instruction	QFN-48
Manufacturer packaging code	485AJ
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	12 weeks
JESD-30 code	S-PQCC-N48
JESD-609 code	e3
length	7 mm
Humidity sensitivity level	1
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	1400 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC48,.28SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
power supply	2.5/3.3 V
Master clock/crystal nominal frequency	50 MHz
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum slew rate	185 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches	1

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NB3M8T3910G

2.5V/3.3V 3:1:10

Configurable Differential

Clock Fanout Buffer with

LVCMOS Reference Output

www.onsemi.com

Description

The NB3M8T3910G is a 3:1:10 Clock fanout buffer operating on a

2.5 V/3.3 V Core V

and a flexible 2.5 V / 3.3 V V

DDO

supply

DDO

≤

A 3:1 MUX selects between Crystal oscillator inputs, or either of

two differential Clock inputs capable of accepting LVPECL, LVDS,

HCSL, or SSTL levels. The MUX select lines, SEL0 and SEL1, accept

LVCMOS or LVTTL levels and select input per Table 3. The Crystal

input is disabled when a Clock input is selected.

Differential Outputs consist of two banks of five differential outputs

with each bank independently mode configurable as LVPECL, LVDS

or HCSL. Each bank of differential output pairs is configured with a

pair of SMODEAx/Bx select lines using LVCMOS or LVTTL levels

per Table 6. Clock input levels and outputs states are determined per

Table 5.

The Single−Ended LVCMOS Output, REFOUT, is synchronously

enabled by the OE_SE control line per Table 4 using LVCMOS /

LVTTL levels. For Clock frequencies above 250 MHz, the REFOUT

line should be disabled.

Features

MARKING

DIAGRAM

1 48

QFN48

G SUFFIX

CASE 485AJ

NB3M8T

3910G

AWLYYWWG

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

ORDERING INFORMATION

See detailed ordering and shipping information on page 19 of

this data sheet.

•

Crystal, Single−Ended or Differential Input Reference

•

Clocks

Differential Input Pair can Accept: LVPECL, LVDS,

HCSL, SSTL

Two Output Banks: Each has Five Differential Outputs

Configurable as LVPECL, LVDS, or HCSL by

SMODEAx/Bx Pins

One Single−Ended LVCMOS Output with Synchronous

OE Control

LVCMOS/LVTTL Interface Levels for all Control

Inputs

Clock Frequency: Up to 1400 MHz, Typical

Output Skew: 50 ps (Max)

Additive RMS Jitter <0.03 ps (156.25 MHz, Typical)

Input to Output Propagation Delay (900 ps Typical)

Operating Supply Modes V

DDO

: 2.5 V/2.5 V,

3.3 V/3.3 V or 3.3 V/2.5 V

•

Industrial Temperature Range −40°C to 85°C

•

This is a Pb−Free Device

Applications

•

Clock Distribution

Telecom

Networking

Backplane

High End Computing

Wireless and Wired Infrastructure

End Products

Servers

Ethernet Switch/Routers

ATE

Test and Measurement

Semiconductor Components Industries, LLC, 2016

March, 2016 − Rev. 2

Publication Order Number:

NB3M8T3910/D

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