On the USB-IF Integrators List: Test ID Number 40000713
Operates at High (480 Mbps) or Full (12 Mbps) Speed
Supports Control Endpoint 0:
❐
Used for handling USB device requests
Supports Four Configurable Endpoints that share a 4-KB
FIFO Space
❐
Endpoints 2, 4, 6, 8 for application-specific control and data
Standard 8- or 16-bit External Master Interface
❐
Glueless interface to most standard microprocessors
DSPs, ASICs, and FPGAs
❐
Synchronous or Asynchronous interface
Integrated Phase-locked Loop (PLL)
3.3V Operation, 5V Tolerant I/Os
56-pin SSOP and QFN Package
Complies with most Device Class Specifications
DSL modems
ATA interface
Memory card readers
Legacy conversion devices
Cameras
Scanners
Home PNA
Wireless LAN
MP3 players
Networking
Printers
■
■
■
■
■
■
■
■
The “Reference Designs” section of the Cypress web site,
www.cypress.com,
provides additional tools for typical USB
applications. Each reference design comes complete with
firmware source code and object code, schematics, and
documentation.
3. Logic Block Diagram
SCL
I2C Bus
Controller
(Master Only)
WAKEUP*
RESET#
SDA
IFCLK*
24 MHz
XTAL
PLL
Read*, Write*, OE*, PKTEND*, CS#
Interrupt#, Ready
SX2 Internal Logic
Flags (3/4)
Address (3)
Control
VCC
1.5K
FIFO
Data
Bus
USB 2.0 XCVR
CY Smart USB
FS/HS Engine
4 KB
FIFO
Data
8/16-Bit Data
DPLUS
DMINUS
Cypress Semiconductor Corporation
Document #: 38-08013 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 07, 2009
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CY7C68001
4. Introduction
The EZ-USB
SX2™
USB interface device is designed to work
with any external master, such as standard microprocessors,
DSPs, ASICs, and FPGAs to enable USB 2.0 support for any
peripheral design. SX2 has a built in USB transceiver and Serial
Interface Engine (SIE), along with a command decoder for
sending and receiving USB data. The controller has four
endpoints that share a 4 KB FIFO space for maximum flexibility
and throughput, and Control Endpoint 0. SX2 has three address
pins and a selectable 8- or 16- bit data bus for command and data
input or output.
Figure 4-1. Example USB System Diagram
5.3 Boot Methods
During the power up sequence, internal logic of the
SX2
checks
for the presence of an I
2
C EEPROM.
[1,2]
If it finds an EEPROM,
it boots off the EEPROM. When the presence of an EEPROM is
detected, the
SX2
checks the value of first byte. If the first byte
is found to be a 0xC4, the
SX2
loads the next two bytes into the
IFCONFIG and POLAR registers, respectively. If the fourth byte
is also 0xC4, the
SX2
enumerates using the descriptor in the
EEPROM, then signals to the external master when enumeration
is complete through an ENUMOK interrupt (See
“Interrupt
System”
on page 3.). If no EEPROM is detected, the
SX2
relies
on the external master for the descriptors. After this descriptor
information is received from the external master, the
SX2
connects to the USB and enumerates.
5.3.1 EEPROM Organization
W indows/U S B C apable H ost
The valid sequence of bytes in the EEPROM are displayed in the
following table.
Table 5-1. Descriptor Length Set to 0x06: Default
Enumeration
USB
C able
Byte Index
U S B C onnection
Description
0xC4
IFCONFIG
POLAR
0xC4
Descriptor Length (LSB):0x06
Descriptor Length (MSB): 0x00
VID (LSB)
VID (MSB)
PID (LSB)
PID (MSB)
DID (LSB)
DID (MSB)
0
1
2
C ypress
S X2
R A M /R O M
D evice C P U
EEPROM
3
4
5
6
7
8
9
A pplication
5. Functional Overview
5.1 USB Signaling Speed
SX2
operates at two of the three rates defined in the
Universal
Serial Bus Specification Revision 2.0,
dated April 27, 2000:
■
■
10
11
Table 5-2. Descriptor Length Not Set to 0x06
Byte Index
0
1
2
3
4
5
6
7
8
0xC4
IFCONFIG
POLAR
0xC4
Descriptor Length (LSB)
Descriptor Length (MSB
Descriptor[0]
Descriptor[1]
Descriptor[2]
Description
Full speed, with a signaling bit rate of 12 Mbits/s
High speed, with a signaling bit rate of 480 Mbits/s.
SX2
does not support the low speed signaling rate of 1.5 Mbits/s.
5.2 Buses
SX2
features:
■
■
A selectable 8- or 16-bit bidirectional data bus
An address bus for selecting the FIFO or Command Interface.
Notes
1. Because there is no direct way to detect which EEPROM type (single or double address) is connected,
SX2
uses the EEPROM address pins A2, A1, and A0 to
determine whether to send out one or two bytes of address. Single-byte address EEPROMs (24LC01, etc.) should be strapped to address 000 and double-byte
EEPROMs (24LC64, etc.) should be strapped to address 001.
2. The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected. Typical pull up values are 2.2K–10K
Ohms.
Document #: 38-08013 Rev. *J
Page 2 of 45
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CY7C68001
■
IFCONFIG:
The IFCONFIG byte contains the settings for the
IFCONFIG register. The IFCONFIG register bits are defined in
IFCONFIG Register 0x01
on page 17. If the external master
requires an interface configuration different from the default,
that interface can be specified by this byte.
POLAR:
The Polar byte contains the polarity of the FIFO flag
pin signals. The POLAR register bits are defined in
POLAR
Register 0x04
on page 18. If the external master requires signal
polarity different from the default, the polarity can be specified
by this byte.
Descriptor:
The Descriptor byte determines if the
SX2
loads
the descriptor from the EEPROM. If this byte = 0xC4, the
SX2
loads the descriptor starting with the next byte. If this byte does
not equal 0xC4, the
SX2
waits for descriptor information from
the external master.
Descriptor Length:
The Descriptor length is within the next
two bytes and indicate the length of the descriptor contained
within the EEPROM. The length is loaded least significant byte
(LSB) first, then most significant byte (MSB).
Byte Index 6 Starts Descriptor Information:
The descriptor
can be a maximum of 500 bytes.
■
■
■
■
Endpoint 2: Bulk out, 512 bytes in high speed mode, 64 bytes
in full speed mode
Endpoint 4: Bulk out, 512 bytes in high speed mode, 64 bytes
in full speed mode
Endpoint 6: Bulk in, 512 bytes in high speed mode, 64 bytes in
full speed mode
Endpoint 8: Bulk in, 512 bytes in high speed mode, 64 bytes in
full speed mode.
■
■
The entire default descriptor is listed in
Default Descriptor
on
page 37 of this data sheet.
5.4 Interrupt System
5.4.1 Architecture
The
SX2
provides an output signal that indicates to the external
master that the
SX2
has an interrupt condition, or that the data
from a register read request is available. The
SX2
has six
interrupt sources: SETUP, EP0BUF, FLAGS, ENUMOK,
BUSACTIVITY, and READY. Each interrupt can be enabled or
disabled by setting or clearing the corresponding bit in the
INTENABLE register.
When an interrupt occurs, the INT# pin is asserted, and the
corresponding bit is set in the Interrupt Status Byte. The external
master reads the Interrupt Status Byte by strobing SLRD/SLOE.
This presents the Interrupt Status Byte on the lower portion of the
data bus (FD[7:0]). Reading the Interrupt Status Byte automati-
cally clears the interrupt. Only one interrupt request occurs at a
time; the
SX2
buffers multiple pending interrupts.
If the external master has initiated a register read request, the
SX2
buffers interrupts until the external master has read the
data. This insures that after a read sequence has begun, the next
interrupt that is received from the
SX2
indicates that the corre-
sponding data is available. Following is a description of this
INTENABLE register.
5.4.2 INTENABLE Register Bit Definition
Bit 7: SETUP
If this interrupt is enabled, and the
SX2
receives a setup packet
from the USB host, the
SX2
asserts the INT# pin and sets bit 7
in the Interrupt Status Byte. This interrupt only occurs if the setup
request is not one that the
SX2
automatically handles. For
complete details on how to handle the SETUP interrupt, refer to
Endpoint 0
on page 8 of this data sheet.
■
■
5.3.2 Default Enumeration
An optional default descriptor can be used to simplify enumer-
ation. Only the Vendor ID (VID), Product ID (PID), and Device ID
(DID) need to be loaded by the
SX2
for it to enumerate with this
default setup. This information is either loaded from an EEPROM
in the case when the presence of an EEPROM (Table
5-1)
is
detected, or the external master may simply load a VID, PID, and
DID when no EEPROM is present. In this default enumeration,
the
SX2
uses the in-built default descriptor (refer to
Default
Descriptor
on page 37).
If the descriptor length loaded from the EEPROM is 6,
SX2
loads
a VID, PID, and DID from the EEPROM and enumerate. The
VID, PID, and DID are loaded LSB, then MSB. For example, if
the VID, PID, and DID are 0x0547, 0x1002, and 0x0001, respec-
tively, then the bytes should be stored as:
■
0x47, 0x05, 0x02, 0x10, 0x01, 0x00.
If there is no EEPROM,
SX2
waits for the external master to
provide the descriptor information. To use the default descriptor,
the external master must write to the appropriate register (0x30)
with descriptor length equal to 6 followed by the VID, PID, and
DID. Refer to
Default Enumeration
on page 8 for further infor-
mation on how the external master may load the values.
The default descriptor enumerates the following endpoints:
Document #: 38-08013 Rev. *J
Page 3 of 45
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CY7C68001
Bit 6: EP0BUF
If this interrupt is enabled, and the Endpoint 0 buffer becomes
available to the external master for read or write operations, the
SX2
asserts the INT# pin and sets bit 6 in the Interrupt Status
Byte. This interrupt is used for handling the data phase of a setup
request. For complete details on how to handle the EP0BUF
interrupt, refer to
Endpoint 0
on page 8 of this data sheet.
Bit 5: FLAGS
If this interrupt is enabled, and any OUT endpoint FIFO’s state
changes from empty to not empty and from not empty to empty,
the
SX2
asserts the INT# pin and sets bit 5 in the Interrupt Status
Byte. This is an alternate way to monitor the status of OUT
endpoint FIFOs instead of using the FLAGA-FLAGD pins, and
can be used to indicate when an OUT packet has been received
from the host.
Bit 2: ENUMOK
If this interrupt is enabled and the
SX2
receives a
SET_CONFIGURATION request from the USB host, the
SX2
asserts the INT# pin and sets bit 2 in the Interrupt Status Byte.
This event signals the completion of the
SX2
enumeration
process.
Bit 1: BUSACTIVITY
If this interrupt is enabled, and the
SX2
detects either an absence
or resumption of activity on the USB bus, the
SX2
asserts the
INT# pin and sets bit 1 in the Interrupt Status Byte. This usually
indicates that the USB host is either suspending or resuming or
that a self-powered device has been plugged in or unplugged. If
the
SX2
is bus-powered, the external master must put the
SX2
into a low power mode after detecting a USB suspend condition
to be USB-compliant.
Bit 0: READY
If this interrupt is enabled, bit 0 in the Interrupt Status Byte is set
when the
SX2
has powered up and performed a self-test. The
external master should always wait for this interrupt before trying
to read or write to the
SX2,
unless an external EEPROM with a
valid descriptor is present. If an external EEPROM with a valid
descriptor is present, the ENUMOK interrupt occurs instead of
the READY interrupt after power up. A READY interrupt also
occurs if the
SX2
is awakened from a low power mode via the
WAKEUP pin. This READY interrupt indicates that the
SX2
is
ready for commands or data.
5.4.3 Qualify with READY Pin on Register Reads
It is true that all interrupts are buffered after a command read
request has been initiated. However, in very rare conditions,
there might be a situation when there is a pending interrupt
already, when a read request is initiated by the external master.
In this case it is the interrupt status byte that is output when the
external master asserts the SLRD. So, a condition exists where
the Interrupt Status Data Byte can be mistaken for the result of a
command register read request. In order to get around this
possible race condition, the first thing that the external master
must do on getting an interrupt from the
SX2
is check the status
of the READY pin. If the READY is low at the time the INT# was
asserted, the data that is output when the external master
strobes the SLRD is the interrupt status byte (not the actual data
requested). If the READY pin is high at the time when the
interrupt is asserted, the data output on strobing the SLRD is the
actual data byte requested by the external master. So it is
important that the state of the READY pin be checked at the time
the INT# is asserted to ascertain the cause of the interrupt.
5.5 Resets and Wakeup
5.5.1 Reset
An input pin (RESET#) resets the chip. The internal PLL stabi-
lizes after V
CC
has reached 3.3V. Typically, an external RC
network (R = 100 KOhms, C = 0.1
μF)
is used to provide the
RESET# signal. The Clock must be in a stable state for at least
200
μs
before the RESET is released.
5.5.2 USB Reset
When the
SX2
detects a USB Reset condition on the USB bus,
SX2
handles it like any other enumeration sequence. This
means that
SX2
enumerates again and assert the ENUMOK
interrupt to let the external master know that it has enumerated.
The external master is then responsible for configuring the
SX2
for the application. The external master should also check
whether
SX2
enumerated at High or Full speed in order to adjust
the EPxPKTLENH/L register values accordingly. The last initial-
ization task is for the external master to flush all of the
SX2
FIFOs.
5.5.3 Wakeup
The
SX2
exits its low power state when one of the following
events occur:
■
■
USB bus signals a resume. The
SX2
asserts a BUSACTIVITY
interrupt.
The external master asserts the WAKEUP pin. The
SX2
asserts
a READY interrupt
[3]
.
5.6 Endpoint RAM
5.6.1 Size
■
■
Control endpoint: 64 Bytes: 1 × 64 bytes (Endpoint 0).
EP2, 4, 6, 8–Eight 512-byte buffers, bulk, interrupt, or isoch-
ronous. EP2 and EP6 can be either double-, triple-, or
quad-buffered. EP4 and EP8 can only be double-buffered. For
high speed endpoint configuration options, see
Figure 8-1.
on
page 11.
Note
3. If the descriptor loaded is set for remote wakeup enabled and the host does a set feature remote wakeup enabled, then the SX2 logic performs RESUME signalling
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