backplane clocks and provides jitter filtered output
clocks for SONET/SDH, PDH and Ethernet network
interface cards
Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
Meets the SONET/SDH jitter generation
requirements up to OC-192/STM-64
Two independent DPLLs provides timing for the
transmit path (backplane to line rate) and the
receive path (recovered line rate to backplane)
Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz,
3.5 Hz, 1.7 Hz, or 0.1 Hz
Supports automatic hitless reference switching and
short term holdover during loss of reference inputs
Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Ethernet PHYs
•
Ordering Information
ZL30146GGG
64 Pin CABGA
Trays
ZL30146GGG2 64 Pin CABGA*
Trays
*Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
Programmable output synthesizer to generate
telecom clock frequencies from any multiple of
8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3)
Generates several styles of output frame pulse
with selectable pulse width, polarity, and frequency
Configurable input to output delay and output to
output phase alignment
Configurable through a serial interface (SPI or I
2
C)
DPLLs can be configured to provide synchronous
or asynchronous clock outputs
July 2009
•
•
•
•
•
•
•
•
•
•
•
Applications
•
•
ITU-T G.8262 Line Cards which support 1 GbE
and 10 GbE interfaces
SONET/SDH line cards up to OC-192/STM-64
osci
osco
ref0
ref1
ref2
ref3
ref4
Input
Ports
ref
m
Rx DPLL
Program m able
Synthesizer
N*8kHz
p_clk
p_fp
sync0
ref
n
/sync
n
Tx DPLL
Ref/Sync
Monitors
Ethernet/
SONET
APLL
diff
apll_clk
m ode
hold lock
I2C/SPI
JTAG
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30146
1.0
Functional Description
Short Form Data Sheet
The ZL30146 OC-192/STM-64 PDH/SONET/SDH/Synchronous Ethernet Network Interface Synchronizer is a
highly integrated device that provides timing for both PDH/SONET/SDH and Ethernet network interface cards. A
functional block diagram is shown in Figure 1.
This device is ideally suited for designs that require both a transmit timing path (backplane to PHY) and a receive
timing path (PHY to backplane). Each path is controlled with separate DPLLs (Tx DPLL, Rx DPLL) which are both
independently configurable through the serial interface (SPI or I
2
C). A typical application of the ZL30146 is shown
in Figure 2. In this application, the ZL30146 translates the 19.44 MHz clock from the telecom rate backplane
(system timing bus), translates the frequency to 622.08 MHz or 156.25 MHz for the PHY Tx clock, and filters the
jitter to ensure compliance with the related standards. On the receive path, the Rx DPLL and the programmable
synthesizer translate the line recovered clock (8 kHz or 25 MHz) from the PHY to the 19.44 MHz telecom
backplane (line recovered timing) for the central timing cards. The ZL30146 allows easy integration of Ethernet line
rates with today’s telecom backplanes.
B IT S A
B IT S B
C e n tra l
T im in g
C a rd
S P
P S
C e n tra l
T im in g
C a rd
ZL30142
DPLL
XO VER
DPLL
ZL30142
P
S
1 9 .4 4 M H z
1 9 .4 4 M H z
S
P
L in e R e c o v e r e d T im in g
P
A
S y s te m T im in g B u s
1 9 .4 4 M H z
A
B
B
A
1 9 .4 4 M H z
B
S
T e le c o m
B a c k p la n e
P ro g
S yn th
ZL30146
Tx
DPLL
Tx
DPLL
ZL30146
P ro g
S y n th
Rx
DPLL
Rx
DPLL
APLL
8 kHz
PHY
O C -1 9 2
L in e C a rd
6 2 2 .0 8 M H z
APLL
1 5 6 .2 5 M H z
PHY
25 M Hz
10G bE
L in e C a rd
Figure 2 - Typical Application of the ZL30146
2
Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2005 All rights reserved.
Package Code
Previous package codes
ISSUE
ACN
DATE
APPRD.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
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However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
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suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I
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C components conveys a license under the Philips I
2
C Patent rights to use these components in and I
2
C System, provided that the system
conforms to the I
2
C Standard Specification as defined by Philips.
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