E2L0029-17-Y1
¡ Semiconductor
MSM514221B
¡ Semiconductor
262,263-Word
¥
4-Bit Field Memory
This version: Jan. 1998
MSM514221B
Previous version: Dec. 1996
DESCRIRTION
The OKI MSM514221B is a high performance 1-Mbit, 256K
¥
4-bit, Field Memory. It is designed
for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital
movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity
TVs and VTRs, exclusively. The MSM514221B is not designed for the other use or high end use
in medical systems, professional graphics systems which require long term picture, and data
storage systems and others. The 1-Mbit capacity fits one field of a conventional NTSC TV screen.
Each of the 4-bit planes has separate serial write and read ports. These employ independent
control clocks to support asynchronous read and write operations. Different clock rates are also
supported that allow alternate data rates between write and read data streams.
The MSM514221B provides high speed FIFO, First-In First-Out, operation without external
refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the
users.
Moreover, fully static type memory cells and decoders for serial access enable refresh free serial
access operation, so that the serial read and/or write control clock can be halted high or low for
any duration as long as the power is on. Internal conflicts of memory access and refreshing
operations are prevented by special arbitration logic.
The MSM514221B's function is simple, and similar to a digital delay device whose delay-bit-
length is easily set by reset timing. The delay length, number of read delay clocks between write
and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256
¥
4-bit enable high
speed first-bit-access with no clock delay just after the write or read reset timings.
The MSM514221B is similar in operation and functionality to OKI 2-Mbit Field Memory
MSM518221.
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¡ Semiconductor
MSM514221B
FEATURES
• Single power supply: 5 V
±10%
• 512 Rows
¥
512 Column
¥
4 bits
• Fast FIFO (First-in First-out)operation
• High speed asynchronous serial access
Read/Write cycle time
30 ns/40 ns/60 ns
Access time
25 ns/30 ns/50 ns
• Functional compatibility with OKI MSM518221
• Self refresh (No refresh control is required)
• Package options:
16-pin 300 mil plastic DIP
(DIP16-P-300-2.54-W1)
26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27)
20-pin 400 mil plastic ZIP
(ZIP20-P-400-1.27)
(Product : MSM514221B-xxRS)
(Product : MSM514221B-xxJS)
(Product : MSM514221B-xxZS)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM514221B-30RS
MSM514221B-40RS
MSM514221B-60RS
MSM514221B-30JS
MSM514221B-40JS
MSM514221B-60JS
MSM514221B-30ZS
MSM514221B-40ZS
MSM514221B-60ZS
Access Time (Max.)
25 ns
30 ns
50 ns
25 ns
30 ns
50 ns
25 ns
30 ns
50 ns
Cycle Time (Min.)
30 ns
40 ns
60 ns
30 ns
40 ns
60 ns
30 ns
40 ns
60 ns
400 mil 20-pin ZIP
300 mil 26/20-pin SOJ
300 mil 16-pin DIP
Package
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¡ Semiconductor
MSM514221B
PIN CONFIGURATION (TOP VIEW)
WE 1
RSTW 2
SWCK 3
D
IN
0 4
D
IN
1 5
D
IN
2 6
D
IN
3 7
V
SS
8
16 V
CC
15 RE
14 RSTR
13 SRCK
12 D
OUT
0
11 D
OUT
1
10 D
OUT
2
9 D
OUT
3
16-Pin Plastic DIP
RSTW 2
SWCK 3
Pin Name
SWCK
SRCK
WE
RE
RSTW
RSTR
D
IN
0 - 3
D
OUT
0 - 3
V
CC
V
SS
NC
WE 1
D
IN
0 4
NC 5
NC 9
D
IN
1 10
D
IN
2 11
D
IN
3 12
V
SS
13
26/20-Pin Plastic SOJ
Serial Write Clock
Serial Read Clock
Write Enable
Read Enable
Write Reset Clock
Read Reset Clock
Data Input
Data Output
Ground (0 V)
No Connection
26 V
CC
SRCK
RE
WE
SWCK
NC
1
3
5
7
9
25 RE
2 RSTR
4 V
CC
6 RSTW
8 D
IN
0
NO LEAD
24 RSTR
23 SRCK
22 NC
18 NC
17 D
OUT
0
16 D
OUT
1
15 D
OUT
2
14 D
OUT
3
NC 11
D
IN
1 13
D
IN
3 15
D
OUT
3 17
D
OUT
1 19
12 NC
14 D
IN
2
16 V
SS
18 D
OUT
2
20 D
OUT
0
20-Pin Plastic ZIP
Function
Power Supply (5 V)
3/15
¡ Semiconductor
MSM514221B
BLOCK DIAGRAM
D
OUT
(¥ 4)
RE
RSTR
SRCK
Data-Out
Buffer (¥4)
Serial
Read
Controller
512 Word Serial Read Register (¥ 4)
Read Line Buffer
Low-Half (¥ 4)
Read Line Buffer
High-Half (¥ 4)
256 (¥ 4)
256 (¥ 4)
120 Word
Sub-Register (¥ 4)
120 Word
Sub-Register (¥ 4)
256K (¥ 4)
Memory
Array
X
Decoder
Read/Write
and Refresh
Controller
256 (¥ 4)
256 (¥ 4)
Clock
Oscillator
Write Line Buffer Write Line Buffer
Low-Half (¥ 4)
High-Half (¥ 4)
512 Word Serial Write Register (¥ 4)
V
BB
Generator
Serial
Write
Controller
Data-In
Buffer (¥ 4)
D
IN
(¥ 4)
WE
RSTW
SWCK
4/15
¡ Semiconductor
MSM514221B
OPERATION
Write Operation
The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset
operation or RSTW.
Each write operation, which begins after RSTW, must contain at least 130 active write cycles, i.e.
SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time
is stored in the serial data registers attached to the DRAM array, an RSTW operation is required
after the last SWCK cycle.
Write Reset : RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address counters
to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write
reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states
of WE are ignored in the write reset cycle.
Before RSTW may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
Data Inputs : D
IN
0 - 3
Write Clock : SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write
address pointer. Data-in setup time t
DS
, and hold time t
DH
are referenced to the rising edge of
SWCK.
Write Enable : WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low
level disables the input and holds the internal write address pointer. There are no WE disable
time (low) and WE enable time (high) restrictions, because the MSM514221B is in fully static
operation as long as the power is on. Note that WE setup and hold times are referenced to the
rising edge of SWCK.
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