High Performance ISM Band
ASK/FSK/GFSK Transmitter IC
ADF7011
FEATURES
Single Chip Low Power UHF Transmitter
Frequency Band
433 MHz to 435 MHz
868 MHz to 870 MHz
On-Chip VCO and Fractional-N PLL
2.3 V to 3.6 V Supply Voltage
Programmable Output Power
–16 dBm to +12 dBm, 0.3 dB Steps
Data Rates up to 76.8 kbps
Low Current Consumption
29 mA at +10 dBm at 433.92 MHz
Power-Down Mode (<1 A)
24-Lead TSSOP Package Hooks to External VCO for
< 1.4 GHz Operation
APPLICATIONS
Low Cost Wireless Data Transfer
Wireless Metering
Remote Control/Security Systems
Keyless Entry
GENERAL DESCRIPTION
The ADF7011 is a low power OOK/ASK/FSK/GFSK UHF
transmitter designed for use in ISM band systems. It contains
and integrated VCO and
Σ-∆
fractional-N PLL. The output
power, channel spacing, and output frequency are program-
mable with four 24-bit registers. The fractional-N PLL enables
the user to select any channel frequency within the European
433 MHz and 868 MHz bands, allowing the use of the ADF7011
in frequency hopping systems. The fractional-N also allows the
transmitter to operate in the less congested sub-bands of the
868 MHz to 870 MHz SRD band.
It is possible to choose from the four different modulation
schemes: Binary or Gaussian Frequency Shift Keying (FSK/
GFSK), Amplitude Shift Keying (ASK), or On/Off Keying
(OOK). The device also features a crystal compensation register
that can provide
±
1 ppm resolution in the output frequency.
Indirect temperature compensation of the crystal can be accom-
plished inexpensively using this register.
Control of the four on-chip registers is via a simple 3-wire inter-
face. The devices operate with a power supply ranging from
2.3 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
C
REG
OSC1
OSC2
CLK
OUT
CPV
DD
CP
GND
CP
OUT
VCO
IN
C
VCO
VCO
GND
CLK
OOK/ASK
V
DD
VCO
DV
DD
PA
RF
OUT
RF
GND
R
PFD/
CHARGE
PUMP
C
REG
LDO
REGULATOR
FRACTIONAL-N
FSK/GFSK
SIGMA-DELTA
LOCK DETECT
D
GND
OOK/ASK
TxCLK
TxDATA
LE
DATA
CLK
CE
SERIAL
INTERFACE
FREQUENCY
COMPENSATION
CENTER
FREQUENCY
MUXOUT
MUXOUT
R
SET
ADF7011
A
GND
TEST
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADF7011–SPECIFICATIONS
Parameter
RF CHARACTERISTICS
Output Frequency Ranges
Lower SRD Band
Upper SRD Band
Phase Frequency Detector Frequency
TRANSMISSION PARAMETERS
Transmit Rate
2
FSK
ASK
GFSK
Frequency Shift Keying
FSK Separation
3
Gaussian Filter t
Amplitude Shift Keying Depth
On/Off Keying
Output Power (No Filtering)
4
868 MHz
433 MHz
Output Power Variation
Max Power Setting
Max Power Setting
Max Power Setting
Programmable Step Size
–16 dBm to +12 dBm
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
Control Clock Input
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
CLK
OUT
Rise/Fall Time
CLK
OUT
Mark: Space Ratio
POWER SUPPLIES
Voltage Supply
DV
DD
Transmit Current Consumption
433 MHz
0 dBm (1 mW)
10 dBm (10 mW)
868 MHz
0 dBm (1 mW)
3 dBm (2 mW)
10 dBm (10 mW)
Crystal Oscillator Block Current
Consumption
Regulator Current Consumption
Power-Down Mode
Low Power Sleep Mode
Min
433
868
3.4
1
(V
DD
= 2.3 V to 3.6 V, GND = 0 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical specifications are at V
DD
= 3 V, T
A
= 25 C, FPFD = 4 MHz @ 433 MHz,
FPFD = 22.1184/5.)
Typ
Max
Unit
435
870
20
MHz
MHz
MHz
0.3
0.3
0.3
1
4.88
0.5
76.8
9.6
76.8
110
620
28
40
3
10
kbits/s
kbits/s
kbits/s
kHz using 3.625 MHz PFD
kHz using 20 MHz PFD
dB
dB
dBm
dBm
dBm V
DD
= 3.6 V
dBm V
DD
= 3.0 V
dBm V
DD
= 2.3 V
dB
V
V
µA
pF
MHz
V, I
OH
= 500
µA
V, I
OL
= 500
µA
ns F
CLK
= 4.8 MHz into 10 pF
9
12
11
9.5
0.3125
0.7
V
DD
0.2
1
10
50
V
DD
DV
DD
– 0.4
0.4
16
50:50
2.3
3.6
V
17
29
19
20.5
34
190
280
0.2
1
mA
mA
mA
mA
mA
µA
µA
µA
–2–
REV. 0
ADF7011
Parameter
PHASE-LOCKED LOOP
VCO Gain 433 MHz/868 MHz
Phase Noise (In-Band)
5
433 MHz
Phase Noise (Out-of-Band)
6
Phase Noise (In-Band)
7
868 MHz
Phase Noise (Out-of-Band)
8
Spurious
9, 10
47–74, 87.5–118, 174–230, 470–862 MHz
9 kHz – 1 GHz
Above 1 GHz
Harmonics
10
Second Harmonic, 433 MHz/868 MHz
Third Harmonic, 433 MHz/868 MHz
Other Harmonics, 433 MHz/868 MHz
REFERENCE INPUT
Crystal Reference
433 MHz
868 MHz
External Oscillator
Frequency
Input Level, High Voltage
Input Level, Low Voltage
FREQUENCY COMPENSATION
Pull In Range of Register
PA CHARACTERISTICS
RF Output Impedance
868 MHz
433 MHz
TIMING INFORMATION
Chip Enabled to Regulator Ready
10
Crystal Oscillator to CLK
OUT
OK
4 MHz Crystal
22.1184 MHz Crystal
TEMPERATURE RANGE – T
A
–40
Min
Typ
40/80
–81
–90
–83
–95
Max
Unit
MHz/V @ 868 MHz
dBc/Hz @ 5 kHz offset
dBc/Hz @ 1 MHz offset
dBc/Hz @ 5 kHz offset
dBc/Hz @ 1 MHz offset
100 kHz loop BW
–54
–36
–30
–23/–28
–25/–29
–26/–40
–20/–23
–22/–25
–23/–35
dBm
dBm
dBm. Assumes external harmonic filter.
dBc
dBc
dBc
1.7
3.4
3.4
0.7 V
DD
22.1184
22.1184
40
0.2 V
DD
MHz
MHz
MHz
V
V
ppm
1
100
16 – j33
25 – j2.6
50
1.8
2.2
+85
200
, Z
REF
= 50
, Z
REF
= 50
µs
ms
ms
C
NOTES
1
Operating temperature range is as follows: –40 C to +85 C.
2
Datarates should be limited to adhere to edge of band requirements in accordance with ETSI 300-220
3
Frequency Deviation = (PFD Frequency Mod Deviation )/2
12
.
GFSK Frequency Deviation = (PFD Frequency 2
m)
/2
12
where
m
= Mod Control.
4
The output power is limited by the spurious requirements of ETSI at +55 C. The addition of an output filter (see Applications section) will allow increased output
levels to >10 dBm at both 433 MHz and 868 MHz
5
V
DD
= 3 V, PFD = 4 MHz, PA = 10 dBm
6
V
DD
= 3 V, Loop Filter BW = 100 kHz
7
V
DD
= 3 V, PFD = 4.42368 MHz, PA = 3 dBm
8
V
DD
= 3 V, Loop Filter BW = 100 kHz
9
These spurious levels are based on a maximum output power of +3 dBm for 868 MHz and +10 dBm for 433 MHz. It assumes a PFD frequency of <5 MHz.
Recommended PFD frequencies are 4.42368 MHz (22.1184/5) for 868 MHz, and 4 MHz for 433 MHz operation. Compliance for higher output powers will require
an external filter. See Applications section.
10
Not production tested. Based on characterization.
Specifications subject to change without notice.
REV. 0
–3–
ADF7011
TIMING CHARACTERISTICS
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
Limit at
T
MIN
to T
MAX
(B Version)
10
10
25
25
10
20
(V
DD
= 3 V
10%; VGND = 0 V, T
A
= 25 C, unless otherwise noted.)
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
Guaranteed by design but not production tested.
Specifications subject to change without notice.
t
3
t
4
CLOCK
t
1
t
2
DATA
DB23 (MSB)
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
LE
t
5
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C, unless otherwise noted.)
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high performance RF integrated circuit with an ESD rating of
<1 kV and is ESD sensitive. Proper precautions should be taken for handling and
assembly.
3
GND = VCOGND = CPGND = RFGND = DGND = AGND = 0 V.
V
DD
to GND
3
. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to + 7 V
CPV
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to + 7 V
Digital I/O Voltage to GND . . . . . . . –0.3 V to DV
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C
TSSOP
JA
Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
ORDERING GUIDE
Model
ADF7011BRU
ADF7011BRU-REEL
ADF7011BRU-REEL7
Temperature
Range
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
Package Option
RU-24 (TSSOP)
RU-24 (TSSOP)
RU-24 (TSSOP)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADF7011 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. 0
ADF7011
PIN CONFIGURATION
R
SET 1
CPV
DD 2
CP
GND 3
CP
OUT
DATA
CLK
LE
4
24
C
REG
23
C
VCO
22
VCO
IN
TSSOP
21
A
GND
20
RF
OUT
19
RF
GND
18
DV
DD
17
TEST
16
VCO
GND
15
OSC1
14
OSC2
13
CLK
OUT
CE
5
6
7
8
ADF7011
TOP VIEW
(Not to Scale)
TxDATA
9
TxCLK
10
MUXOUT
11
D
GND 12
PIN FUNCTION DESCRIPTIONS
Pin No.
1
Mnemonic
R
SET
Function
External Resistor to Set Change Pump Current and Some Internal Bias Currents. Use 4.7 kΩ as default:
I
CP MAX
=
9.5
R
SET
So, with
R
SET
= 4.7 kΩ,
I
CP MAX
= 2.02 mA.
2
3
4
5
6
7
8
9
10
11
CPV
DD
CP
GND
CP
OUT
CE
DATA
CLK
LE
TxDATA
TxCLK
MUXOUT
Charge Pump Supply. This should be biased at the same level as RF
OUT
and DV
DD
. The pin should be
decoupled with a 0.1
µF
capacitor as close to the pin as possible.
Charge Pump Ground.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.
Chip Enable. A logic low applied to this pin powers down the part. This must be high for the part to
function. This is the only way to power down the regulator circuit.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a
high impedance CMOS input.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches, the latch being selected using the control bits.
Digital data to be transmitted is input on this pin.
GFSK Only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the
ADF7011. The clock is provided at the same frequency as the data rate.
This multiplexer output allows either the digital lock detect (most common), the scaled RF, or the scaled
reference frequency to be accessed externally. Used commonly for system debug. See the Function Regis-
ter Map.
Ground Pin for the RF Digital Circuitry.
The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be used to drive the clock
input of a microcontroller. To reduce spurious components in the output spectrum, the sharp edges can
be reduced with a series RC. For 4.8 MHz output clock, a series 50
Ω
into 10 pF will reduce spurs to
< –50 dBc. Defaults on power-up to divide by 16.
Oscillator Pin. If a single-ended reference (such as a TCXO) is used, it should be applied to this pin.
When using an external signal generator, a 51
Ω
resistor should be tied from this pin to ground. The
XOE
bit in the R register should set high when using an external reference.
12
13
D
GND
CLK
OUT
14
OSC2
REV. 0
–5–
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