Features
•
16-Mbit (x16) Flash and 4-megabit SRAM
•
2.7V to 3.3V Operating Voltage
•
Low Operating Power
– 40 mA Operating Current (Maximum)
– 35 µA Standby Current (Maximum)
•
Industrial Temperature Range
Flash
•
2.7V to 3.3V Read/Write
•
Access Time – 70 ns, 90 ns
•
Sector Erase Architecture
•
•
– Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
Fast Word Program Time – 12 µs
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 12 mA Active
– 13 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
Top/Bottom Boot Block Configuration
128-bit Protection Register
Minimum 100,000 Erase Cycles
•
•
•
•
•
•
•
•
16-megabit
Flash +
4-megabit
SRAM Stack
Memory
AT52BR1664A
AT52BR1664AT
SRAM
•
•
•
•
•
4-megabit (256K x 16)
2.7V to 3.3V V
CC
Operating Voltage
70 ns Access Time
Fully Static Operation and Tri-state Output
1.2V (Min) Data Retention
Device Number
AT52BR1664A(T)
Flash Configuration
16M (1M x 16)
SRAM Configuration
4M (256K x 16)
Rev. 3361C–STKD–1/04
1
CBGA Top View
1
2
3
4
5
6
7
8
9
10
11
12
A
NC
NC
NC
A11
A15
A14
A13
A12
GND
NC
NC
NC
B
A16
A8
A10
A9
I/O15
SWE
I/O14
I/O7
C
WE
RDY BUSY
I/O13
I/O6
I/O4
I/O5
D
SGND
RESET
I/O12
SCS2
SVcc
Vcc
E
NC
Vpp
A19
I/O11
I/O10
I/O2
I/O3
F
SLB
SUB
SOE
I/O9
I/O8
I/O0
I/O1
G
A18
A17
A7
A6
A3
A2
A1
SCS1
H
NC
NC
NC
A5
A4
A0
CE
GND
OE
NC
NC
NC
Pin
Configurations
Pin Name
A0 - A17
A18 - A19
CE
OE/SOE
WE/SWE
VCC
VPP
I/O0-I/O15
SCS1, SCS2
RDY/BUSY
SVCC
GND/SGND
SUB
SLB
NC
RESET
Function
Flash/SRAM Common Address Input for 4M SRAM
Flash Address Input
Flash Chip Enable
Flash/SRAM, Output Enable
Flash/SRAM, Write Enable
Flash Power Supply
Optional Flash Power Supply for Faster Program/Erase Operations
Data Inputs/Outputs
SRAM Chip Select
Flash Ready/Busy Output
SRAM Power Supply
Flash/SRAM GND
SRAM Upper Byte
SRAM Lower Byte
No Connect
Flash Reset
2
AT52BR1664A(T)
3361C–STKD–1/04
AT52BR1664A(T)
Description
The AT52BR1664A(T) combines a single plane 16-Mbit Flash and a 4-megabit SRAM in a stacked 66-ball CBGA package.
Both devices operate at 2.7V to 3.3 in the industrial temperature range.
Block Diagram
ADDRESS
OE WE
SOE SWE
RESET
CE
FLASH
RDY/BUSY
SRAM
SCS1
SCS2
SUB
SLB
DATA
Absolute Maximum Ratings
Temperature under Bias.................................. -40° C to +85° C
Storage Temperature .................................... -55° C to +150° C
All Input Voltages
except V
PP
and RESET
(including NC Pins)
with Respect to Ground .....................................-0.2V to +3.3V
Voltage on V
PP
with Respect to Ground ..................................-0.2V to + 6.25V
Voltage on RESET
with Respect to Ground ...................................-0.2V to +13.5V
All Output Voltages
with Respect to Ground .....................................-0.2V to +0.2V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC and AC Operating Range
AT52BR1664A(T)-70, -90
Operating Temperature (Case)
V
CC
Power Supply
Industrial
-40° C - 85° C
2.7V to 3.3V
3
3361C–STKD–1/04
16-Mbit Flash Memory Block Diagram
I/O0 - I/O15
OUTPUT
BUFFER
INPUT
BUFFER
OUTPUT
MULTIPLEXER
A0 - A19
INPUT
BUFFER
DATA
REGISTER
IDENTIFIER
REGISTER
STATUS
REGISTER
COMMAND
REGISTER
CE
WE
OE
RESET
ADDRESS
LATCH
DATA
COMPARATOR
RDY/BUSY
WRITE STATE
MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
GND
X-DECODER
MAIN
MEMORY
4
AT52BR1664A(T)
3361C–STKD–1/04
AT52BR1664A(T)
16-Mbit Flash
Description
The 16-Mbit Flash is organized as 1,048,576 words of 16 bits each. The x16 data appears on
I/O0 - I/O15. The memory is divided into 39 sectors for erase operations. The device has CE
and OE control signals to avoid any bus contention. This device can be read or reprogrammed
using a single power supply, making it ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector (see “Sector Lockdown” section).
To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend
feature. This feature will put the erase or program on hold for any amount of time and let the
user read data from or program data to any of the remaining sectors within the memory. The
end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by
the toggle bit.
The VPP pin provides data protection. When the V
PP
input is below 0.4V, the program and
erase functions are inhibited. When V
PP
is at 0.9V or above, normal program and erase opera-
tions can be performed.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement
of entering the three-byte program sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the write control lines are required for
writing into the device. This mode (Single Pulse Word Program) is exited by powering down
the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back
to V
CC
. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not
work while in this mode; if entered they will result in data being programmed into the device. It
is not recommended that the six-byte code reside in the software of the final product but only
exist in external programming code.
5
3361C–STKD–1/04
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