HN29V1G91T-30
128M
×
8-bit AG-AND Flash Memory
REJ03C0056-0400Z
Rev. 4.00
Jul.20.2004
Description
The HN29V1G91 series achieves a write speed of 10 Mbytes/sec, which is 5 times faster than Renesas's
previous multi level cell Flash memory, using 0.13µm process technology and AG-AND (Assist Gate-
AND) type Flash memory cell using multi level cell technology provides both the most cost effective
solution and high speed programming.
Features
•
On-board single power supply: V
CC
= 2.7 V to 3.6 V
•
Operation Temperature range: Ta = 0 to +70°C
•
Memory organization
Memory array: (2048+64) bytes
×
16384 page
×
4 Bank
Page size: (2048+64) bytes
Block size: (2048+64) bytes
×
2 page
Page Register: (2048+64) bytes
×
4 Bank
•
Multi level memory cell
2bit/cell
•
Automatic program
Page program
Multi bank program
Cache program
2 page cache program
•
Automatic Erase
Block Erase
Multi Bank Block Erase
•
Access time
Memory array to register (1st access time): 120
µs
max
Serial access: 35 ns min
Rev.4.00, Jul.20.2004, page 1 of 89
HN29V1G91T-30
•
Low power dissipation
Read I
CC1
(50 ns cycle): 10 mA (typ)
Read I
CC2
(35 ns cycle): 15 mA (typ)
Program I
CC3
(single bank): 10 mA (typ)
Program I
CC4
(Multi bank): 20 mA (typ)
Erase I
CC5
(single bank): 10 mA (typ)
Erase I
CC6
(Multi bank): 15 mA (typ)
Standby I
SB1
(TTL): 1 mA (max)
Standby I
SB2
(CMOS): 50
µA
(max)
Deep Standby I
SB3
: 5
µA
(max)
•
Program time: 600
µs
(typ) (Single/Multi bank)
transfer rate: 10 MB/s (Multi bank)
•
Erase time: 650
µs
(typ) (Single/Multi bank)
•
The following architecture is required for data reliability
Error correction: 3 bit error correction per 512byte are recommended.
Block replacement: When an error occurs in program page, block replacement including
corresponding page should be done. When an error occurs in erase operation, future access to this
bad block is prohibited. It is required to manage it creating a table or using another appropriate
scheme by the system (Valid blocks: Initial valid blocks for more than 98% per Bank.
Replacement blocks must be ensured more than 1.8% of valid blocks per Bank).
Wear leveling: Wear leveling is to level Program and Erase cycles in one block in order to reduce
the burden for one block and let the device last for long time. Actually, it does detect the block
which is erased and rewritten many times and replace it with less accessed block.
To secure 10
5
cycles as the program/erase endurance, need to control not to exceed Program and
Erase cycles to one block. You should adopt wear leveling once in 5000 Program and Erase cycles.
It is better to program it as a variable by software.
•
Program/Erase Endurance: 10
5
cycles
•
Package line up
TSOP: TSOP Type-I 48pin package (TFP-48DA)
Ordering Information
Type No.
HN29V1G91T-30
Operating voltage (V
CC
)
2.7 V to 3.6 V
Organization
×8
Package
12.0
×
20.00 mm
0.5 mm pitch
48-pin plastic TSOPI (TFP-48DA)
2
Rev.4.00, Jun.20.2004, page 2 of 89
HN29V1G91T-30
Pin Arrangement
48-pin TSOP
RES
NC
NC
NC
NC
NC
R/B
RE
CE
NC
NC
V
CC
V
SS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
PRE
V
CC
V
SS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
(Top view)
Pin configuration
Pin name
I/O 1 to I/O 8
CLE
ALE
CE
RE
WE
WP
R/B
PRE
RES
V
CC
V
SS
NC
Function
Command, address, data Input/output
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready/Busy
Power on Auto Read Enable
Reset
Power
Ground
No Connection
Rev.4.00, Jun.20.2004, page 3 of 89
HN29V1G91T-30
Memory map and address
Memory Map
FFFFH
FFFEH
FFFDH
1Page = (2048+64)Bytes: Program Size
1Block = (2048+64)Bytes x 2Pages: Erase Size
= (4096+128)Bytes: Erase Size
1Device = (2048+64)Bytes x 2Pages x 32768Blocks
0006H
0005H
0004H
0003H
0002H
0001H
0000H
2048bytes
Data register
2048bytes
64bytes
Block 2
Block 1
Block 0
64bytes
Bank Organization
Bank0
(8192Blocks)
(16384pages)
Block 0
page 0
page 4
Block 4
page 8
page 12
Bank1
(8192Blocks)
(16384pages)
Block 1
page 1
page 5
Block 5
page 9
page 13
Bank2
(8192Blocks)
(16384pages)
Block 2
page 2
page 6
Block 6
page 10
page 14
Bank3
(8192Blocks)
(16384pages)
Block 3
page 3
page 7
Block 7
page 11
page 15
Block 32764
page 65528
page 65532
Block 32765
page 65529
page 65533
Block 32766
page 65530
page 65534
Block 32767
page 65531
page 65535
Addressing
Symbol
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
CA1
CA2
RA1
RA2
I/O8
A7
L
A19
A27
I/O7
A6
L
A18
A26
I/O6
A5
L
A17
A25
I/O5
A4
L
A16
A24
I/O4
A3
A11
A15
A23
I/O3
A2
A10
A14
A22
I/O2
A1
A9
A13
A21
I/O1
A0
A8
Column
address
A12 Row
A20 address
A12, A13: Bank select
A14: Page select
A15 to A27: Block select
Rev.4.00, Jun.20.2004, page 5 of 89
Microcontroller MCU
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