AD7942BCPWP datasheet, PDF - EEWORLD Datasheet

Preliminary Technical Data

FEATURES

14-bit resolution with no missing codes

Throughput: 250 kSPS

INL: ±0.4 LSB typ, ±1 LSB max (±0.0061 % of FSR)

S/(N + D): 85 dB @ 20 kHz

THD: −100 dB @ 20 kHz

Pseudo-differential analog input range

0 V to V

REF

with V

REF

up to VDD

No pipeline delay

Single-supply 5V operation with

1.8 V/2.5 V/3 V/5 V logic interface

Serial interface SPI®/QSPI™/µWire/DSP compatible

Daisy chain multiple ADCs and BUSY indicator

Power dissipation

1.15 mW @ 2.5 V/100 kSPS, 3.3 mW @ 5 V/100 kSPS,

1.15 µW @ 2.5 V/100 SPS

Stand-by current: 1 nA

10-lead package: MSOP (MSOP-8 size) and

3 mm × 3 mm QFN (LFCSP) (SOT-23 size)

Pin-for-pin compatible with the 16-Bit AD7685

14-Bit, 250 kSPS PulSAR™

ADC in MSOP/QFN

AD7942

APPLICATION DIAGRAM

0.5 TO 5V

2.5V to 5V

0 TO VREF

IN+

IN–

REF VDD

VIO

SDI

1.8 TO VDD

3- OR 4-WIRE INTERFACE

(SPI, DAISY CHAIN, CS)

AD7942

GND

SCK

SDO

CNV

Figure 1.

GENERAL DESCRIPTION

The AD7942 is a 14-bit, charge redistribution successive

approximation, analog-to-digital converter (ADC) that operates

from a single 5V power supply, VDD. It contains a low power,

high speed, 14-bit sampling ADC with no missing codes, an

internal conversion clock, and a versatile serial interface port.

The part also contains a low noise, wide bandwidth, short

aperture delay track-and-hold circuit. On the CNV rising edge,

it samples an analog input IN+ between 0 V to REF with respect

to a ground sense IN−. The reference voltage, REF, is applied

externally and can be set up to the supply voltage.

Its power scales linearly with throughput.

The SPI compatible serial interface also features the ability,

using the SDI input, to daisy chain several ADCs on a single 3-

wire bus and provides an optional BUSY indicator. It is

compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate

supply VIO.

The AD7942 is housed in a 10-lead MSOP or a 10-lead QFN

(LFCSP) with operation specified from −40°C to +85°C.

APPLICATIONS

Battery-powered equipment

Data acquisition

Instrumentation

Medical instruments

Process control

Table 1. MSOP, QFN (LFCSP)/SOT-23 14 and16-Bit ADC

Type

16-Bit True

Differential

16-Bit Pseudo

Differential/Unipolar

16-Bit Unipolar

14-Bit Pseudo

Differential/Unipolar

14-Bit Unipolar

100 kSPS

AD7684

AD7683

AD7680

AD7942

AD7940

AD7946

250 kSPS

AD7687

AD7685

AD7694

500 kSPS

AD7688

AD7686

Rev Pr B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

AD7942

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Terminology ...................................................................................... 9

Typical Performance Characteristics ........................................... 10

Circuit Information.................................................................... 13

Preliminary Technical Data

Converter Operation.................................................................. 13

Typical Connection Diagram ................................................... 14

Digital Interface.......................................................................... 18

Application Hints ........................................................................... 25

Layout .......................................................................................... 25

Evaluating the AD7942’s Performance .................................... 25

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 27

REVISION HISTORY

8/04—Revision B: Preliminary

Rev Pr B | Page 2 of 28

Preliminary Technical Data

SPECIFICATIONS

VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V

REF

= VDD, T

A

= –40°C to +85°C, unless otherwise noted.

Table 2.

Parameter

RESOLUTION

ANALOG INPUT

Voltage Range

Absolute Input Voltage

Analog Input CMRR

Leakage Current at 25°C

Input Impedance

ACCURACY

No Missing Codes

Differential Linearity Error

Integral Linearity Error

Transition Noise

Gain Error

2

, T

MIN

to T

MAX

Gain Error Temperature Drift

Offset Error

2

, T

MIN

to T

MAX

Offset Temperature Drift

Power Supply Sensitivity

THROUGHPUT

Conversion Rate

Transient Response

AC ACCURACY

Signal-to-Noise

Spurious-Free Dynamic Range

Total Harmonic Distortion

Signal-to-(Noise + Distortion)

Conditions

Min

14

0

−0.1

65

1

See the Analog Input section.

14

−0.7

−1

REF = VDD = 5 V

Typ

Max

AD7942

Unit

Bits

V

dB

nA

IN+ − IN−

IN+

IN−

f

IN

= 250 kHz

Acquisition Phase

V

REF

VDD + 0.1

0.1

VDD = 5V

±

5%

VDD = 4.5 V to 5.5 V

VDD = 2.3 V to 4.5 V

Full-Scale Step

f

IN

= 20 kHz, V

REF

= 5 V

f

IN

= 20 kHz, V

REF

= 2.5 V

f

IN

= 20 kHz

f

IN

= 20 kHz

f

IN

= 20 kHz, V

REF

= 5 V

f

IN

= 20 kHz, V

REF

= 5 V, −60 dB

Input

f

IN

= 20 kHz, V

REF

= 2.5 V

0

±0.25

±0.4

0.33

±TBD

+0.7

+1

±TBD

Bits

LSB

1

LSB

ppm/°C

mV

ppm/°C

LSB

kSPS

µs

dB

3

dB

250

200

1.8

85

84

−100

85

25

84

TBD

83

Intermodulation Distortion

4

1

2

LSB means least significant bit. With the 5 V input range, one LSB is 305.2 µV.

See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.

3

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

4

f

IN1

= 21.4 kHz, f

IN2

= 18.9 kHz, each tone at −7 dB below full-scale.

Rev Pr B | Page 3 of 28

AD7942

Table 3.

Parameter

REFERENCE

Voltage Range

Load Current

SAMPLING DYNAMICS

−3 dB Input Bandwidth

Aperture Delay

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format

Pipeline Delay

V

OL

V

OH

POWER SUPPLIES

VDD

VIO

VIO Range

Standby Current

1, 2

Power Dissipation

Conditions

Min

0.5

250 kSPS, REF = 5 V

Preliminary Technical Data

VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V

REF

= VDD, T

A

= –40°C to +85°C, unless otherwise noted.

Typ

Max

VDD + 0.3

TBD

2

2.5

Unit

V

µA

MHz

ns

VDD = 5 V

–0.3

0.7 × VIO

−1

0.3 × VIO

VIO + 0.3

+1

V

µA

I

SINK

= +500 µA

I

SOURCE

= −500 µA

Specified Performance

VDD and VIO = 5 V, 25°C

VDD = 2.5 V, 100 SPS Throughput

VDD = 2.5 V, 100 kSPS Throughput

VDD = 2.5 V, 200 kSPS Throughput

VDD = 5 V, 100 kSPS Throughput

VDD = 5 V, 250 kSPS Throughput

T

MIN

to T

MAX

Serial 14 Bits Straight Binary

Conversion Results Available Immediately

after Completed Conversion

0.4

VIO − 0.3

2.3

1.8

1

1.15

2.25

3.3

5.5

VDD + 0.3

50

2

4

5

12.5

+85

V

nA

µW

mW

°C

TEMPERATURE RANGE

3

Specified Performance

−40

1

2

With all digital inputs forced to VIO or GND as required.

During acquisition phase.

3

Contact Analog Devices for extended temperature range.

Rev Pr B | Page 4 of 28

Preliminary Technical Data

TIMING SPECIFICATIONS

−40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

Table 4. VDD = 4.5 V to 5.5 V

1

Conversion Time: CNV Rising Edge to Data Available

Acquisition Time

Time between Conversions

CNV Pulse Width ( CS Mode )

SCK Period ( CS Mode )

SCK Period ( Chain Mode )

VIO above 4.5 V

VIO above 3 V

VIO above 2.7 V

VIO above 2.3 V

SCK Low Time

SCK High Time

SCK Falling Edge to Data Remains Valid

SCK Falling Edge to Data Valid Delay

VIO above 4.5 V

VIO above 3 V

VIO above 2.7 V

VIO above 2.3 V

CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO above 4.5 V

VIO above 2.7 V

VIO above 2.3 V

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)

SDI Valid Setup Time from CNV Rising Edge (CS Mode)

SDI Valid Hold Time from CNV Rising Edge (CS Mode)

SCK Valid Setup Time from CNV Rising Edge (Chain Mode)

SCK Valid Hold Time from CNV Rising Edge (Chain Mode)

SDI Valid Setup Time from SCK Falling Edge (Chain Mode)

SDI Valid Hold Time from SCK Falling Edge (Chain Mode)

SDI High to SDO High (Chain Mode with BUSY indicator)

VIO above 4.5 V

VIO above 2.3 V

1

AD7942

Symbol

t

CONV

t

ACQ

t

CYC

t

CNVH

t

SCK

t

SCK

Min

0.5

1.8

4

10

15

19

20

21

22

7

5

Typ

Max

2.2

Unit

µs

ns

t

SCKL

t

SCKH

t

HSDO

t

DSDO

14

15

16

17

t

EN

15

18

22

25

15

0

5

4

15

26

ns

t

DIS

t

SSDICNV

t

HSDICNV

t

SSCKCNV

t

HSCKCNV

t

SSDISCK

t

HSDISCK

t

DSDOSDI

See

Error! Reference source not found.

and

Error! Reference source not found.

for load conditions.

Rev Pr B | Page 5 of 28

AD7942BCPWP

AD7942BCPWP Overview

Preview

AD7942BCPWP Related Products

Recommended Resources