AFE8201
SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005
IF Analog-to-Digital Converter
with Digital Downconverter
FEATURES
D
D
12-BIT, 80MSPS ADC
INTEGRATED DIGITAL DOWNCONVERTER (DDC):
DESCRIPTION
The AFE8201 consists of a general-purpose, 80MSPS,
12-bit analog-to-digital converter (ADC), a digital
downconverter (DDC), and user-programmable digital
filters. It is designed to sample narrowband (2.5MHz or
less) IF signals and digitally mix, filter, and decimate the
signals to baseband.
The DDC consists of a digital quadrature mixer followed
by a CIC decimation filter and FIR filters. The mixer
frequency and initial phase are independently
programmed by 32-bit control words.
D
D
D
D
D
Quadrature Mixer/NCO
CIC Decimation Filter
FIR Filters
MIXER: 32-BIT FREQUENCY AND PHASE
DECIMATION RATIO: 32 to 4096
USER PROGRAMMABLE FIR FILTERS WITH
16-BIT COEFFICIENTS
12-BIT AUXILIARY DAC
DATA INTERFACE COMPATIBLE WITH TI C5x/C6x
DSP BUFFERED SERIAL PORT (McBSP):
D
D
D
D
D
D
D
D
Code Composer Module for Easy Software
Generation
SPI CONTROL INTERFACE
3.3V ANALOG, 1.8V DIGITAL SUPPLY
1.8V to 3.3V I/O SUPPLY
TQFP-48
APPLICATIONS
SOFTWARE RADIOS
IF RECEIVE CHANNEL
DIGITAL RADIO RECEIVERS
NARROWBAND RECEIVERS
Following the first FIR filter are two parallel FIR filters
that can be used to provide two output streams or
interleaved to form one extended filter with up to 262
taps. The AFE8201 also contains a 12-bit
general-purpose auxiliary digital-to-analog converter
(DAC) for applications such as AGC amplifier control.
Control register data as well as decimation filter
coefficients are written to the AFE8201 through the
industry-standard SPI control interface. The baseband
output signals are transported through a general-
purpose, high-speed serial interface that is compatible
with TI C5x/C6x DSP family buffered serial ports
(McBSP).
IFP
IFM
12−
Bit
Pipeline
ADC
DOUT0
Quadrature
Mixer
CIC Filter
N
FIR Filter 1
2
FIR Filter 2A
2
Data Interface
DOUT1
DFSO
DCLK
DIN
NCO
FIR Filter 2B
2
AUX
Auxiliary
DAC
DFSI
Voltage
Reference
Clock
Interface
Timing
Generator
SPI Control
Interface
REFM VCM REFP VGB
MCLK
MCLKB
PWD
SYNC RST_N
SCK
MOSI MISO CS_N
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these
products without notice.
Copyright
2003−2005, Texas Instruments Incorporated
www.ti.com
PRODUCT PREVIEW
After the CIC filter, the internal I and Q signals are
passed on to the first FIR filter, which can implement
even, odd, halfband, and arbitrary impulse responses
with up to 62 taps using 16-bit coefficients.
AFE8201
www.ti.com
SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005
ORDERING INFORMATION
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
PFB
SPECIFIED
TEMPERATURE
RANGE
−40°C to +85°C
PACKAGE
MARKING
AFE8201
ORDERING
NUMBER
AFE8201PFBT
AFE8201
TQFP-48
AFE8201PFBR
TRANSPORT MEDIA,
QUANTITY
Tape and Reel, 250
Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the
TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
Supply Voltage Range:
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 4V
DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 2.3V
IOVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 3.6V
Voltage Between AGND and DGND . . . . . . . . . . . . . −0.3V to 0.5V
Voltage Between AVDD to DVDD . . . . . . . . . . . . . . . −3.3V to 3.3V
Digital Inputs(2) . . . . . . . . . . . . . . . . . . . . . . . −0.3V to DVDD + 0.3V
Digital Output Data . . . . . . . . . . . . . . . . . . . . −0.3V to DVDD + 0.3V
Operating Free-Air Temperature Range. TA . . . . . . −40°C to 85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . −55°C to +125°C
(1) Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only; functional operation of the device at these or any
other conditions beyond those indicated under the
Recommended Operating Conditions is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may
affect device reliability.
(2) Measured with respect to DGND.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PRODUCT PREVIEW
RECOMMENDED OPERATING CONDITIONS
MIN
Supplies and References
Operating Free-Air Temperature, TA
Analog Supply Voltage, AVDD
Digital Supply Voltage, DVDD
Output Driver Supply Voltage, IOVDD
Input Common-Mode Voltage
Differential Input Voltage Range
Clock Inputs: MCLK and MCLKB
Sample Rate, fS
Differential Input Mode Voltage Input Swing
Differential Input Common-Mode Voltage
Single-Ended Mode High-Level Input Voltage, VIHC
Single-Ended Mode Low-Level Input Voltage, VILC
Clock Pulse Width High, tW(H)
Clock Pulse Width Low, tW(L)
Digital Inputs
High-Level Input Voltage, VIH
Low-Level Input Voltage, VIL
0.7
×
IOVDD
0.25
×
IOVDD
V
V
5.625
5.625
6.25
6.25
2
0.8
5
0.4
1.65
80
3.3
MHz
V
V
V
V
ns
ns
−40
3.15
1.6
1.6
VCM
2
3.3
1.8
85
3.45
2.0
3.6
°C
V
V
V
V
VPP
TYP
MAX
UNITS
2
AFE8201
www.ti.com
SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005
AUXILIARY DAC CHARACTERISTICS
All specifications at +25°C, AVDD = +3.3V, and DVDD = +1.8V, unless otherwise noted.
PARAMETER
Resolution
Input code 0x000
Output voltage range
Output impedance
Settling time
Offset
Gain error
DC
performance
Differential nonlinearity, DNL
Integral nonlinearity, INL
Power-supply rejection ratio, PSRR
Ensured monotonic
After correcting for gain and offset errors
Input code 0x400, AVDD = 3.15VDC to 3.45VDC
to 0.1% FSR
±1
±5
±0.5
±2
60
Input code 0xFFF
CONDITIONS
MIN
TYP
12
0.0
2.75
1
10
MAX
UNIT
bits
V
V
kΩ
µs
% of FSR
% of FSR
LSB
LSB
dB
RECEIVE CHANNEL CHARACTERISTICS
All specifications at +25°C, fS = 80MSPS, AVDD = +3.3V, DVDD = +1.8V, IOVDD = +3.3V, Gain = 1, Decimation Ratio = 80, Internal Digital
Filter Bandwidth = 264kHz, and Input Signal = 10.7MHz, unless otherwise noted.
PARAMETER
DC Accuracy
Input impedance
Differential nonlinearity, DNL
Integral nonlinearity, INL
Offset error
Gain error
Gain = 1
Gain = 1.14
Gain = 1.33
Full-scale input level (peak differential)
Gain = 1.6
Gain = 2.0
Gain = 2.67
Gain = 4.0
Gain change settling time
Power-supply rejection ratio, PSRR
References
Negative reference, VREFN
Positive reference, VREFP
Common-mode voltage, VCM
AC Performance
Input 455kHz, −1dBFS
Spurious-free dynamic range, SFDR
2nd-order harmonic, HD2
Input 10.7MHz, −1dBFS
Input 10.7MHz, −1dBFS
Input 455kHz, −1dBFS
Signal-to-noise ratio, SNR
Aperture delay
Aperture uncertainty
Power Supply
Analog supply voltage, AVDD
Digital supply voltage, DVDD
Output driver supply voltage, IOVDD
Normal operation
Power dissipation
Digital I/O supply current
Digital supply current
Analog supply current
Power-down
3.15
1.71
3.15
3.3
1.8
3.3
490
20
7
72
103
3.45
1.89
3.45
570
V
V
V
mW
mW
mA
mA
mA
Input 10.7MHz, −1dBFS
In 3kHz bandwidth, −1dBFS, 10.7MHz, 20kHz from fundamental
70
76
76
86
80
75
74
102
2
0.2
dBc
dBc
dBc
dB
dB
dB
ns
ps
1.1
2.1
1.25
2.25
1.8
1.4
2.4
V
V
V
Number of samples to achieve rated accuracy
AVDD = 3.15VDC to 3.45VDC
−0.0244
−0.0244
6.25
±0.0122
±0.012
3
1
1.0
0.875
0.75
0.625
0.5
0.375
0.25
2
70
+0.0244
+0.0244
kΩ
%FSR
%FSR
mV
%FS
V
V
V
V
V
V
V
Samples
dB
CONDITIONS
MIN
TYP
MAX
UNIT
3
PRODUCT PREVIEW
AFE8201
www.ti.com
SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005
DIGITAL INTERFACE SPECIFICATIONS
All specifications at +25°C, AVDD = 3.3V, DVDD = 1.8V, and VDDS = 3.3V, unless otherwise noted.
PARAMETER
High Level Input Current, IIH
Low-Level Input Current, IIL
High-Level Output Voltage, VOH
Low-Level Output Voltage, VOL
CONDITIONS
VIH = 1.6V to 3.6V
VIL = 0V to 0.4V
IOH = −50µA
IOL = 50µA
MIN
−10
−10
0.8
×
IOVDD
0.2
×
IOVDD
TYP
MAX
10
10
UNITS
µA
µA
V
V
DATA INTERFACE TIMING
DCLKO
DFSO
DOUT0
IA[15]
IA[14]
IA[13]
IA[12]
DOUT1
IB[15]
t
d1
t
d2
t
d3
IB[14]
IB[13]
IB[12]
PRODUCT PREVIEW
Figure 1. Data Interface Timing 1
PARAMETER
DCLKO to DFSO Delay, td1
DCLKO to DOUT0 Delay, td2
DCLKO to DOUT1 Delay, td3
CONDITIONS
MIN
−0.4
−0.2
−0.2
TYP
MAX
3.2
2.5
2.5
UNITS
ns
ns
ns
DCLKO
DFSI
DIN
t
su1
t
h1
t
su2
D[15]
D[14]
D[13]
D[12]
t
h2
Figure 2. Data Interface Timing 2
PARAMETER
DFSI to DCLKO Setup Time, tsu1
DFSI to DCLKO Hold Time, th1
DIN to DCLKO Setup Time, tsu2
DIN to DCLKO Hold Time, th2
CONDITIONS
MIN
1.2
0.4
1.0
0.4
TYP
MAX
UNITS
ns
ns
ns
ns
4
AFE8201
www.ti.com
SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005
CONTROL INTERFACE TIMING
SCK
CS_N
MOSI
MISO
t
L
t
su3
t
h3
t
d4
t
T
t
I
Figure 3. Control Interface Timing
PARAMETER
Maximum SCK Frequency
CS_N Leading Time, tL
CS_N Trailing Time, tT
CS_N Idle Time, tL
MOSI to SCK Setup Time, tsu3
MOSI to SCK Hold Time, th3
SCK to MISO Delay Time, td4
Leading CS_N to Trailing CS_N
Trailing CS_N to Leading SCK
Trailing SCK to Leading CS_N
5.0
5.0
5.0
5.0
1.0
1.0
8.0
CONDITIONS
MIN
TYP
MAX
1
UNITS
MHz
ns
ns
ns
ns
ns
5
PRODUCT PREVIEW
ns
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