Features ................................................................................................................................................................ 6
Data Path Logic............................................................................................................................................ 8
Initialization State Machine .......................................................................................................................... 8
Signal Descriptions ............................................................................................................................................... 8
Using the Local User Interface.............................................................................................................................. 9
Initialization and Auto-Refresh Control....................................................................................................... 10
Command and Address ............................................................................................................................. 11
Data Write .................................................................................................................................................. 12
Data Read .................................................................................................................................................. 13
Read/Write with Auto Precharge................................................................................................................ 13
Type Tab ............................................................................................................................................................. 20
Bank Size ................................................................................................................................................... 22
User Slot Size ............................................................................................................................................ 22
EMR Prog During Init ................................................................................................................................. 22
Auto Refresh Burst Count .......................................................................................................................... 22
External Auto Refresh Port ........................................................................................................................ 22
Info Tab ............................................................................................................................................................... 24
Chapter 4. IP Core Generation............................................................................................................. 25
Licensing the IP Core.......................................................................................................................................... 25
Getting Started .................................................................................................................................................... 25
IPexpress-Created Files and Top Level Directory Structure............................................................................... 27
Simulation Files for Core Evaluation ................................................................................................................... 30
Testbench Top ........................................................................................................................................... 30
Obfuscated Core Simulation Model ........................................................................................................... 30
Memory Model ........................................................................................................................................... 31
Memory Model Parameter.......................................................................................................................... 31
Enabling Hardware Evaluation in Diamond................................................................................................ 31
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 31
Updating/Regenerating the IP Core .................................................................................................................... 31
Regenerating an IP Core in Diamond ........................................................................................................ 31
Regenerating an IP Core in ispLEVER ...................................................................................................... 32
I/O Types for DDR...................................................................................................................................... 34
Telephone Support Hotline ........................................................................................................................ 41
E-mail Support ........................................................................................................................................... 41
Local Support ............................................................................................................................................. 41
Internet ....................................................................................................................................................... 41
Revision History .................................................................................................................................................. 42
Appendix A. Resource Utilization ....................................................................................................... 43
Ordering Part Number................................................................................................................................ 43
IPUG93_1.2, March 2015
4
DDR & DDR2 for MachXO2 PLD Family User’s Guide
Chapter 1:
Introduction
The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-
purpose memory controller that interfaces with industry standard DDR/DDR2 memory devices/modules and pro-
vides a generic command interface to user applications. This core reduces the efforts required to integrate the
DDR/DDR2 memory controller with the remainder of the application and minimizes the need to deal with the
DDR/DDR2 memory interface. This core utilizes dedicated DDR input and output registers in the Lattice devices to
meet the requirements for high-speed double data rate transfers. The timing parameters for a memory device or
module can be set through the signals that are input to the core as a part of the configuration interface. This capa-
bility enables effortless switching among different memory devices by updating the timing parameters to suit the
application without generating a new core configuration.
Throughout this user’s guide, the term ‘DDR’ is used to represent the first-generation DDR memory. Since this doc-
ument covers both the Lattice DDR and DDR2 memory controller IP cores, use of the term ‘DDR’ indicates both
DDR and DDR2.
Quick Facts
Table 1-1 gives quick facts about the DDR IP core for MachXO2™ devices.
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