Data Sheet
FEATURES
8-channel, 24-bit simultaneous sampling analog-to-digital
converter (ADC)
Single-ended or true differential inputs
Programmable gain amplifier (PGA) per channel (gains of
1, 2, 4, and 8)
Low dc input current
±1.5 nA (differential)
±4 nA (single-ended)
Up to 16 kSPS output data rate (ODR) per channel
Programmable ODRs and bandwidth
Sample rate converter (SRC) for coherent sampling
Sampling rate resolution up to 15.2 µSPS
Low latency sinc3 filter path
Adjustable phase synchronization
Internal 2.5 V reference
Two power modes optimizing power dissipation and
performance: high resolution mode and low power mode
Low resolution successive approximation (SAR) ADC for
system and chip diagnostics
Power supply
Bipolar (±1.65 V) or unipolar (3.3 V) supplies
Digital input/output (I/O) supply: 1.8 V to 3.6 V
Performance temperature range: –40°C to +105°C
Functional temperature range: –40°C to +125°C
Performance
Combined ac and dc performance
108 dB signal-to-noise ratio (SNR)/dynamic range at 16 kSPS
in high resolution mode
−109 dB total harmonic distortion (THD)
±7 ppm integral nonlinearity (INL)
±40 µV offset error
±0.1% gain error
±10 ppm/°C typical temperature coefficient
8-Channel, 24-Bit,
Simultaneous Sampling ADC
AD7779
the signal chain. The
AD7779
accepts V
REF
from 1 V up to 3.6 V.
The analog inputs accept unipolar (0 V to V
REF
/GAIN) or true
bipolar (±V
REF
/GAIN/2 V) analog input signals with 3.3 V or
±1.65 V analog supply voltages. The analog inputs can be
configured to accept true differential, pseudo differential, or single-
ended signals to match different sensor output configurations.
Each channel contains an ADC modulator and a sinc3, low
latency digital filter. An SRC is provided to allow fine resolution
control over the
AD7779
ODR. This control can be used in
applications where the ODR resolution is required to maintain
coherency with 0.01 Hz changes in the line frequency. The SRC
is programmable through the serial port interface (SPI). The
AD7779
implements two different interfaces: a data output
interface and SPI control interface. The ADC data output
interface is dedicated to transmitting the ADC conversion
results from the
AD7779
to the processor. The SPI interface
is used to write to and read from the
AD7779
configuration
registers and for the control and reading of data from the SAR
ADC. The SPI interface can also be configured to output the
Σ-Δ conversion data.
The
AD7779
includes a 12-bit SAR ADC. This ADC can be used
for
AD7779
diagnostics without having to decommission one of
the Σ-Δ ADC channels dedicated to system measurement func-
tions. With the use of an external multiplexer, which can be
controlled through the three general-purpose inputs/outputs pins
(GPIOs), and signal conditioning, the SAR ADC can be used to
validate the Σ-Δ ADC measurements in applications where
functional safety is required. In addition, the
AD7779
SAR ADC
includes an internal multiplexer to sense internal nodes.
The
AD7779
contains a 2.5 V reference and reference buffer.
The reference has a typical temperature coefficient of 10 ppm/°C.
The
AD7779
offers two modes of operation: high resolution
mode and low power mode. High resolution mode provides a
higher dynamic range while consuming 10.75 mW per channel;
low power mode consumes just 3.37 mW per channel at a
reduced dynamic range specification.
The specified operating temperature range is −40°C to +105°C,
although the device is operational up to +125°C.
Note that throughout this data sheet, certain terms are used to
refer to either the multifunction pins or a range of pins. The
multifunction pins, such as DCLK0/SDO, are referred to either
by the entire pin name or by a single function of the pin, for
example, DCLK0, when only that function is relevant. In the
case of ranges of pins, AVSSx refers to the following pins:
AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4.
APPLICATIONS
Circuit breakers
General-purpose data acquisition
Electroencephalography (EEG)
Industrial process control
GENERAL DESCRIPTION
The
AD7779
is an 8-channel, simultaneous sampling ADC.
There are eight full Σ-Δ ADCs on chip. The
AD7779
provides
an ultralow input current to allow direct sensor connection. Each
input channel has a programmable gain stage allowing gains of
1, 2, 4, and 8 to map lower amplitude sensor outputs into the
full-scale ADC input range, maximizing the dynamic range of
Rev. C
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AD7779
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 4
Functional Block Diagram .............................................................. 5
Specifications..................................................................................... 6
DOUTx Timing Characterististics ........................................... 10
SPI Timing Characterististics ................................................... 11
Synchronization Pins and Reset Timing Characteristics ...... 12
SAR ADC Timing Characterististics ....................................... 13
GPIO SRC Update Timing Characterististics......................... 13
Absolute Maximum Ratings .......................................................... 14
Thermal Resistance .................................................................... 14
ESD Caution ................................................................................ 14
Pin Configuration and Function Descriptions ........................... 15
Typical Performance Characteristics ........................................... 18
Terminology .................................................................................... 31
RMS Noise and Resolution............................................................ 33
High Resolution Mode............................................................... 33
Low Power Mode ........................................................................ 33
Theory of Operation ...................................................................... 34
Analog Inputs .............................................................................. 34
Transfer Function ....................................................................... 35
Core Signal Chain....................................................................... 36
Capacitive PGA ........................................................................... 36
Internal Reference and Reference Buffers ............................... 36
Integrated LDOs ......................................................................... 37
Clocking and Sampling .............................................................. 37
Digital Reset and Synchronization Pins .................................. 37
Digital Filtering ........................................................................... 38
Shutdown Mode.......................................................................... 38
Controlling the AD7779 ............................................................ 39
Pin Control Mode....................................................................... 39
SPI Control .................................................................................. 41
Digital SPI Interface ................................................................... 44
Diagnostics and Monitoring ......................................................... 47
Self Diagnostics Error ................................................................ 47
Monitoring Using the AD7779 SAR ADC (SPI Control
Mode) ........................................................................................... 48
Σ-Δ ADC Diagnostics (SPI Control Mode) ............................ 50
Data Sheet
Σ-∆
Output Data ............................................................................. 51
ADC Conversion Output—Header and Data ........................ 51
Sample Rate Converter (SRC) (SPI COntrol MOde) ............ 52
Data Output Interface ................................................................ 54
Calculating the CRC Checksum .............................................. 58
Register Summary .......................................................................... 60
Register Details ............................................................................... 64
Channel 0 Configuration Register ........................................... 64
Channel 1 Configuration Register ........................................... 64
Channel 2 Configuration Register ........................................... 65
Channel 3 Configuration Register ........................................... 65
Channel 4 Configuration Register ........................................... 66
Channel 5 Configuration Register ........................................... 66
Channel 6 Configuration Register ........................................... 67
Channel 7 Configuration Register ........................................... 67
Disable Clocks to ADC Channel Register .............................. 68
Channel 0 Sync Offset Register ................................................ 68
Channel 1 Sync Offset Register ................................................ 68
Channel 2 Sync Offset Register ................................................ 69
Channel 3 Sync Offset Register ................................................ 69
Channel 4 Sync Offset Register ................................................ 69
Channel 5 Sync Offset Register ................................................ 69
Channel 6 Sync Offset Register ................................................ 70
Channel 7 Sync Offset Register ................................................ 70
General User Configuration 1 Register ................................... 70
General User Configuration 2 Register ................................... 71
General User Configuration 3 Register ................................... 72
Data Output Format Register ................................................... 72
Main ADC Meter and Reference Mux Control Register ...... 73
Global Diagnostics Mux Register ............................................. 74
GPIO Configuration Register ................................................... 75
GPIO Data Register.................................................................... 75
Buffer Configuration 1 Register ............................................... 75
Buffer Configuration 2 Register ............................................... 76
Channel 0 Offset Upper Byte Register..................................... 76
Channel 0 Offset Middle Byte Register ................................... 76
Channel 0 Offset Lower Byte Register..................................... 77
Channel 0 Gain Upper Byte Register....................................... 77
Channel 0 Gain Middle Byte Register ..................................... 77
Channel 0 Gain Lower Byte Register ....................................... 77
Rev. C | Page 2 of 100
Data Sheet
Channel 1 Offset Upper Byte Register .....................................78
Channel 1 Offset Middle Byte Register ....................................78
Channel 1 Offset Lower Byte Register .....................................78
Channel 1 Gain Upper Byte Register........................................78
Channel 1 Gain Middle Byte Register ......................................79
Channel 1 Gain Lower Byte Register........................................79
Channel 2 Offset Upper Byte Register .....................................79
Channel 2 Offset Middle Byte Register ....................................79
Channel 2 Offset Lower Byte Register .....................................80
Channel 2 Gain Upper Byte Register........................................80
Channel 2 Gain Middle Byte Register ......................................80
Channel 2 Gain Lower Byte Register........................................80
Channel 3 Offset Upper Byte Register .....................................81
Channel 3 Offset Middle Byte Register ....................................81
Channel 3 Offset Lower Byte Register .....................................81
Channel 3 Gain Upper Byte Register........................................81
Channel 3 Gain Middle Byte Register ......................................82
Channel 3 Gain Lower Byte Register........................................82
Channel 4 Offset Upper Byte Register .....................................82
Channel 4 Offset Middle Byte Register ....................................82
Channel 4 Offset Lower Byte Register .....................................83
Channel 4 Gain Upper Byte Register........................................83
Channel 4 Gain Middle Byte Register ......................................83
Channel 4 Gain Lower Byte Register........................................83
Channel 5 Offset Upper Byte Register .....................................84
Channel 5 Offset Middle Byte Register ....................................84
Channel 5 Offset Lower Byte Register .....................................84
Channel 5 Gain Upper Byte Register........................................84
Channel 5 Gain Middle Byte Register ......................................85
Channel 5 Gain Lower Byte Register........................................85
Channel 6 Offset Upper Byte Register .....................................85
Channel 6 Offset Middle Byte Register ....................................85
Channel 6 Offset Lower Byte Register .....................................86
Channel 6 Gain Upper Byte Register........................................86
Channel 6 Gain Middle Byte Register ......................................86
AD7779
Channel 6 Gain Lower Byte Register ....................................... 86
Channel 7 Offset Upper Byte Register ..................................... 87
Channel 7 Offset Middle Byte Register.................................... 87
Channel 7 Offset Lower Byte Register ..................................... 87
Channel 7 Gain Upper Byte Register ....................................... 87
Channel 7 Gain Middle Byte Register ...................................... 88
Channel 7 Gain Lower Byte Register ....................................... 88
Channel 0 Status Register .......................................................... 88
Channel 1 Status Register .......................................................... 89
Channel 2 Status Register .......................................................... 89
Channel 3 Status Register .......................................................... 90
Channel 4 Status Register .......................................................... 90
Channel 5 Status Register .......................................................... 91
Channel 6 Status Register .......................................................... 91
Channel 7 Status Register .......................................................... 92
Channel 0/Channel 1 DSP Errors Register.............................. 92
Channel 2/Channel 3 DSP Errors Register.............................. 93
Channel 4/Channel 5 DSP Errors Register.............................. 93
Channel 6/Channel 7 DSP Errors Register.............................. 94
Channel 0 to Channel 7 Error Register Enable Register ....... 94
General Errors Register 1 ........................................................... 95
General Errors Register 1 Enable .............................................. 95
General Errors Register 2 ........................................................... 96
General Errors Register 2 Enable .............................................. 96
Error Status Register 1 ................................................................ 97
Error Status Register 2 ................................................................ 97
Error Status Register 3 ................................................................ 98
Decimation Rate (N) MSB Register ......................................... 98
Decimation Rate (N) LSB Register ........................................... 98
Decimation Rate (IF) MSB Register ......................................... 99
Decimation Rate (IF) LSB Register .......................................... 99
SRC Load Source and Load Update Register .......................... 99
Outline Dimensions ......................................................................100
Ordering Guide .........................................................................100
Rev. C | Page 3 of 100
AD7779
REVISION HISTORY
6/2018—Rev. B to Rev. C
Change to t
22B
Parameter, Table 3 ................................................. 11
Changes to AUXAIN± Parameter, Table 7.................................. 14
Changes to Table 17 ........................................................................ 39
Added Figure 104; Renumbered Sequentially ............................ 46
Changes to Figure 115 Caption and Figure 116 Caption .......... 54
Updated Outline Dimensions ..................................................... 100
Changes to Ordering Guide ........................................................ 100
8/2017—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Change to START Pin Description, Table 9 ................................ 15
Changes to Figure 48 ...................................................................... 24
Changes to Digital Reset and Synchronization Pins Section .... 37
Changes to Figure 94 ...................................................................... 38
Changes to Phase Adjustment Section and Table 20 ................. 42
Added Table 21; Renumbered Sequentially ................................ 42
Changes to Digital SPI Interface Section ..................................... 44
9/2016—Rev. 0 to Rev. A
Changes to General Description Section ...................................... 1
Changes to Table 1 ............................................................................ 6
Changes to Table 2 .......................................................................... 10
Changes to Table 4 .......................................................................... 12
Changes to Figure 8 Caption through Figure 13 Caption ......... 18
Changes to Figure 14 Caption and Figure 17 Caption .............. 19
Changes to Figure 22 ...................................................................... 20
Changes to Figure 26 Caption, Figure 27 Caption, Figure 29
Caption, and Figure 30 Caption ................................................... 21
Data Sheet
Changes to Figure 35 Caption ...................................................... 22
Changes to Figure 38 through Figure 43 ..................................... 23
Changes to Figure 44, Figure 45 Caption, and Figure 47 .......... 24
Changes to Figure 51 Caption, Figure 52 Caption, and
Figure 55 Caption ........................................................................... 25
Changes to Figure 56, Figure 58, Figure 59, and Figure 61....... 26
Changes to Figure 63 Caption, Figure 64 Caption, Figure 66
Caption, and Figure 67 Caption ................................................... 27
Changes to Figure 76 and Figure 79 ............................................ 29
Changes to Figure 80 and Figure 81 ............................................ 30
Changes to Figure 100 ................................................................... 44
Changes to SPI SAR Diagnostic Mode (SPI Control Mode)
Section .............................................................................................. 46
Changes to SPI Transmission Errors (SPI Control Mode) ....... 48
Changes to CRC Header Section, Figure 107, and Table 33 to
Table 35 ............................................................................................ 51
Changes to SRC Bandwidth Section ............................................ 52
Changes to Figure 109, Figure 110, SRC Group Delay and
Latency Section, and Setting Time Section ................................. 53
Added Figure 111 and Figure 112; Renumbered Sequentially .....53
Changes to Table 40 ..............................................................................57
Changes to Calculating the CRC Checksum Section and
Table 42 ............................................................................................ 58
Changes to SPI Control Mode Checksum Section .................... 59
Changes to Table 66 ....................................................................... 74
2/2016—Revision 0: Initial Version
Rev. C | Page 4 of 100
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
AVDD1x
COMMON-
MODE
VOLTAGE
2.5V REF
AIN0+
AIN0–
SINC3/
SRC
FILTER
SINC3/
SRC
FILTER
SINC3/
SRC
FILTER
SINC3/
SRC
FILTER
SINC3/
SRC
FILTER
SINC3/
SRC
FILTER
SINC3/
SRC
FILTER
SINC3/
SRC
FILTER
REF_OUT
REFx+ REFx–
AVDD2
AREGxCAP
IOVDD
DREGCAP
VCM
ANALOG
LDO
DIGITAL
LDO
AD7779
XTAL1
CLOCK
MANAGER
XTAL2/MCLK
SYNC_IN
SYNC_OUT
START
280mV p-p
EXT_REF
PGA
Σ-Δ ADC
GAIN
OFFSET
DATA OUTPUT
INTERFACE
DCLK
DRDY
DOUT3
DOUT2
DOUT1
REGISTER MAP
AND
LOGIC CONTROL
DOUT0
RESET
FORMAT1
FORMAT0
HARDWARE
MODE
CONFIGURATION
MODE3/ALERT
MODE2/GPIO2
MODE1/GPIO1
MODE0/GPIO0
INT_REF
AIN1+
AIN1–
PGA
REFERENCES
PGA
REFERENCES
PGA
REFERENCES
PGA
REFERENCES
PGA
REFERENCES
PGA
REFERENCES
PGA
REFERENCES
Σ-Δ ADC
GAIN
OFFSET
AIN2+
AIN2–
Σ-Δ ADC
GAIN
OFFSET
AIN3+
AIN3–
Σ-Δ ADC
GAIN
OFFSET
AIN4+
AIN4–
Σ-Δ ADC
GAIN
OFFSET
AIN5+
AIN5–
Σ-Δ ADC
GAIN
OFFSET
SPI INTERFACE
GAIN
OFFSET
ALERT/CS
DCLK2/SCLK
DCLK1/SDI
DCLK0/SDO
AIN6+
AIN6–
Σ-Δ ADC
AIN7+
AIN7–
AUXAIN+
AUXAIN–
Σ-Δ ADC
GAIN
OFFSET
AD7779
SAR ADC
DIAGNOSTIC
INPUTS
13295-001
AVSSx
AVDD4
CONVST_SAR
Figure 1.
Rev. C | Page 5 of 100
Wireless Connectivity
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