XRA1200/1200P
8-BIT I2C/SMBUS GPIO EXPANDER
SEPTEMBER 2011
REV. 1.0.0
GENERAL DESCRIPTION
The XRA1200/1200P is an 8-bit GPIO expander with
After power-up, the
an I
2
C/SMBus interface.
XRA1200 has internal 100K ohm pull-up resistors on
each I/O pin that can be individually enabled. The
XRA1200P have the internal pull-up resistors
enabled upon power-up in case it is necessary for the
inputs to be in a known state.
In addition, the GPIOs on the XRA1200/1200P can
individually be controlled and configured. As outputs,
the GPIOs can be outputs that are high, low or in
three-state mode. The three-state mode feature is
useful for applications where the power is removed
from the remote devices, but they may still be
connected to the GPIO expander.
As inputs, the internal pull-up resistors can be
enabled or disabled and the input polarity can be
inverted. The interrupt can be programmed for
different behaviors.
The interrupts can be
programmed to generate an interrupt on the rising
edge, falling edge or on both edges. The interrupt
can be cleared if the input changes back to its original
state or by reading the current state of the inputs.
The XRA1200/1200P are enhanced versions of other
8-bit GPIO expanders with an I
2
C/SMBus interface.
The XRA1200 is pin and software compatible with the
CAT9534 and PCA9534. The XRA1200P is pin and
software compatible with the CAT9554 and
PCA9554.
The XRA1200/1200P are also pin
compatible with the PCA9554A and TCA9554A.
The XRA1200/1200P are available in 16-pin QFN
and 16-pin TSSOP packages.
FEATURES
•
1.65V to 3.6V operating voltage
•
8 General Purpose I/Os (GPIOs)
•
5V tolerant inputs
•
Maximum stand-by current of 1uA at +1.8V
•
I
2
C/SMBus bus interface
■
■
■
I
2
C clock frequency up to 400kHz
Noise filter on SDA and SCL inputs
Up to 32 I
2
C Slave Addresses
Internal pull-up resistors
Polarity inversion
Individual interrupt enable
Rising edge and/or Falling edge interrupt
Input filter
Output Level Control
Output Three-State Control
•
Individually programmable inputs
■
■
■
■
■
•
Individually programmable outputs
■
■
•
Open-drain active low interrupt output
•
Pin and software compatible with CAT9534,
CAT9554, PCA9534, and PCA9554
•
3kV HBM ESD protection per JESD22-A114F
•
200mA latch-up performance per JESD78B
APPLICATIONS
•
Personal Digital Assistants (PDA)
•
Cellular Phones/Data Devices
•
Battery-Operated Devices
•
Global Positioning System (GPS)
•
Bluetooth
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRA1200/1200P
REV. 1.0.0
8-BIT I2C/SMBUS GPIO EXPANDER
PIN DESCRIPTIONS
Pin Description
N
AME
QFN-16 TSSOP-16
T
YPE
P
IN
#
P
IN
#
D
ESCRIPTION
I2C INTERFACE
SDA
SCL
IRQ#
A0
A1
A2
GPIOs
P0
P1
P2
P3
P4
P5
P6
P7
2
3
4
5
7
8
9
10
4
5
6
7
9
10
11
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General purpose I/Os P0-P7. All GPIOs are configured as inputs upon power-
up or after a reset. After power-up or reset, the internal pull-up resistors are
enabled for the XRA1200P. The internal pull-up resistors are disabled for the
XRA1200.
13
12
11
15
16
1
15
14
13
1
2
3
I/O
I
OD
I
I
I
I
2
C-bus data input/output (open-drain).
I
2
C-bus serial input clock.
Interrupt output (open-drain, active LOW).
These pins select the I
2
C slave address. See
Table 1
.
ANCILLARY SIGNALS
VCC
GND
GND
14
6
Center
Pad
16
8
-
Pwr
Pwr
Pwr
1.65V to 3.6V VCC supply voltage.
Power supply common, ground.
The exposed pad at the bottom surface of the package is designed for thermal
performance. Use of a center pad on the PCB is strongly recommended for ther-
mal conductivity as well as to provide mechanical stability of the package on the
PCB. The center pad is recommended to be solder masked defined with open-
ing size less than or equal to the exposed thermal pad on the package bottom to
prevent solder bridging to the outer leads of the device. Thermal vias must be
connected to GND plane as the thermal pad of package is at GND potential.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
3
XRA1200/1200P
8-BIT I2C/SMBUS GPIO EXPANDER
1.0 FUNCTIONAL DESCRIPTIONS
1.1
I
2
C-bus Interface
REV. 1.0.0
The I
2
C-bus interface is compliant with the Standard-mode and Fast-mode I
2
C-bus specifications. The I
2
C-bus
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps.
The first byte sent by an I
2
C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is
HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that
contains the address of the register to access. The XRA120x responds to each write with an acknowledge
(SDA driven LOW by XRA1200/1200P for one clock cycle when SCL is HIGH). The last byte sent by an I
2
C-
bus master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See
Figures 3
-
5
below. For complete details, see the I
2
C-bus specifications.
F
IGURE
3. I
2
C S
TART AND
S
TOP
C
ONDITIONS
SDA
SCL
S
START condition
P
STOP condition
F
IGURE
4. M
ASTER
W
RITES
T
O
S
LAVE
S
SLAVE
ADDRESS
W
A
COMM AND
BYTE
A
DATA
BYTE
A
P
W h ite b lo c k : h o s t to X R A 1 2 0 x
G re y b lo c k : X R A 1 2 0 x to h o s t
F
IGURE
5. M
ASTER
R
EADS
F
ROM
S
LAVE
S
SLAVE
ADDRESS
W
A
COMMAND
BYTE
A
S
SLAVE
ADDRESS
R
A
nDATA
A
LAST DATA
NA
P
White block: host to XRA120x
Grey block: XRA120x to host
4
Embedded System
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