S912ZVCA19F0MLF datasheet, PDF

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S912ZVCA19F0MLF: Description16-bit Microcontrollers - MCU 32MHz -40/+125degC AutoQual QFP 48; Categorysemiconductor The embedded processor and controller; File Size3MB，797 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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S912ZVCA19F0MLF Overview

16-bit Microcontrollers - MCU 32MHz -40/+125degC AutoQual QFP 48

S912ZVCA19F0MLF Parametric

Parameter Name	Attribute value
Product Category	16-bit Microcontrollers - MCU
Manufacturer	NXP
RoHS	Details
Core	S12
Data Bus Width	16 bit
Maximum Clock Frequency	20 MHz
Program Memory Size	192 kB
Data RAM Size	12 kB
ADC Resolution	12 bit
Operating Supply Voltage	12 V
Interface Type	CAN, I2C, SPI
Packaging	Bulk
Data RAM Type	SRAM
Data ROM Size	2 kB
Data ROM Type	EEPROM
Minimum Operating Temperature	- 40 C
Moisture Sensitive	Yes
Number of ADC Channels	16 Channel
Number of Timers/Counters	12 Timer
Factory Pack Quantity	1250
Supply Voltage - Max	40 V
Supply Voltage - Min	3.5 V
Watchdog Timers	Watchdog Timer
Unit Weight	0.006288 oz

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MC9S12ZVC-Family

Reference Manual and

Datasheet

S12 MagniV

Microcontrollers

MC9S12ZVCRMV2

Rev. 2.0

26-March-2018

nxp.com

The MC9S12ZVC family of microcontrollers is targeted at use in safety relevant systems and has been developed

using an ISO26262 compliant development system under the NXP Safe Assure Program. For more details of the

NXP Safe Assure program, refer to : NXP Safe Assure

For more details of how to use the device in safety relevant systems refer to the MC9S12ZVC Safety Manual at

nxp.com

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most

current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to

nxp.com/

A full list of family members and options is included in device overview section.

The following revision history table summarizes changes contained in this document.

This document contains information for all constituent modules, with the exception of the S12Z CPU. For S12ZCPU

information please refer to the CPU S12Z Reference Manual.

Revision History

Date

Revision

Level

Rev 1.6

Rev 1.7

Rev 1.8

Rev 1.9

Rev 2.0

Description

Added item 18 and 19 Table E-1 Bandgap voltage and temperature dependency

Changed item 5 Table H-2 ACMP input offset

Added operating condition for C part to Table A-5

Corrected Table 1-1 Two SCIs for 48pin packages. Corrected typo in table H-2 item 5

Corrected Package Information for 64LQFP Exposed Pad

Updated

Appendix A MCU Electrical Specifications

22-August-2016

13-October-2016

2-January-2018

29-January-2018

26-March-2018

NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation or guarantee regarding the suitability of its products

for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including

without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. NXP

does not convey any license under its patent rights nor the rights of others. NXP products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the NXP product could create a situation

where personal injury or death may occur. Should Buyer purchase or use NXP products for any such unintended or unauthorized application, Buyer shall indemnify and hold NXP

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or

indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that NXP was negligent regarding the design or

manufacture of the part.

Chapter 1

Device Overview MC9S12ZVC-Family

1.1

1.2

1.3

1.4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.2.1 MC9S12ZVC-Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.4.1 S12Z Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.4.2 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.4.3 Clocks, Reset and Power Management Unit (CPMU) . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.4.4 Main External Oscillator (XOSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.4.5 Timer (TIM0 and TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.4.6 Pulse Width Modulation Module (PWM0 and PWM1) . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.4.7 Inter-IC Module (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.4.8 CAN Physical Layer (CANPHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.4.9 Multi-Scalable Controller Area Network (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.4.10 SENT Transmitter (SENT_TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.4.11 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.4.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.4.13 Analog-to-Digital Converter Module (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.4.14 Digital-to-Analog Converter Module (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.4.15 Analog Comparator Module (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.4.16 Supply Voltage Sensor (BATS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.4.17 On-Chip Voltage Regulator system (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Family Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.6.1 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Signal Description and Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.7.1 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.7.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.7.3 MODC — Mode C signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.7.4 PAD[15:0] / KWAD[15:0] — Port AD, input pins of ADC . . . . . . . . . . . . . . . . . . . . . . 36

1.7.5 PE[1:0] — Port E I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.7.6 PJ[1:0] — Port J I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.7.7 PL[1:0] / KWL[1:0] — Port L input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.7.8 PP[7:0] / KWP[7:0] — Port P I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.7.9 PS[7:0] / KWS[7:0] — Port S I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.7.10 PT[7:0] — Port T I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.7.11 AN[15:0] — ADC input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.7.12 ACMP Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.7.13 DAC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.7.14 VRH_0, VRH_1, VRL_0, VRL_1 — ADC reference signals . . . . . . . . . . . . . . . . . . . . 38

1.7.15 ETRIG0 — External ADC trigger signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.7.16 SPI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.7.17 SCI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

MC9S12ZVC Family Reference Manual , Rev. 2.0

NXP Semiconductors

1.5

1.6

1.7

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