LatticeECP3 Family Data Sheet
Preliminary DS1021 Version 01.6, March 2010
LatticeECP3 Family Data Sheet
Introduction
November 2009
Preliminary Data Sheet DS1021
Features
Higher Logic Density for Increased System
Integration
• 17K to 149K LUTs
• 133 to 586 I/Os
Embedded SERDES
• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit
SERDES, and 8-bit SERDES modes
• Data Rates 230 Mbps to 3.2 Gbps per channel
for all other protocols
• Up to 16 channels per device: PCI Express,
SONET/SDH, Ethernet (1GbE, SGMII, XAUI),
CPRI, SMPTE 3G and Serial RapidIO
• Dedicated read/write levelling functionality
• Dedicated gearing logic
• Source synchronous standards support
– ADC/DAC, 7:1 LVDS, XGMII
– High Speed ADC/DAC devices
• Dedicated DDR/DDR2/DDR3 memory with DQS
support
• Optional Inter-Symbol Interference (ISI)
correction on outputs
Programmable sysI/O™ Buffer Supports
Wide Range of Interfaces
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
On-chip termination
Optional equalization filter on inputs
LVTTL and LVCMOS 33/25/18/15/12
SSTL 33/25/18/15 I, II
HSTL15 I and HSTL18 I, II
PCI and Differential HSTL, SSTL
LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
Dedicated bank for configuration I/Os
SPI boot flash interface
Dual-boot images supported
Slave SPI
TransFR™ I/O for simple field updates
Soft Error Detect embedded macro
IEEE 1149.1 and IEEE 1532 compliant
Reveal Logic Analyzer
ORCAstra FPGA configuration utility
On-chip oscillator for initialization & general use
1.2V core power supply
sysDSP™
• Fully cascadable slice architecture
• 12 to 160 slices for high performance multiply
and accumulate
• Powerful 54-bit ALU operations
• Time Division Multiplexing MAC Sharing
• Rounding and truncation
• Each slice supports
– Half 36x36, two 18x18 or four 9x9 multipliers
– Advanced 18x36 MAC and 18x18 Multiply-
Multiply-Accumulate (MMAC) operations
Flexible Device Configuration
Flexible Memory Resources
• Up to 6.85Mbits sysMEM™ Embedded Block
RAM (EBR)
• 36K to 303K bits distributed RAM
System Level Support
sysCLOCK Analog PLLs and DLLs
• Two DLLs and up to ten PLLs per device
Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
Table 1-1. LatticeECP3™ Family Selection Guide
Device
LUTs (K)
sysMEM Blocks (18Kbits)
Embedded Memory (Kbits)
Distributed RAM Bits (Kbits)
18X18 Multipliers
SERDES (Quad)
PLLs/DLLs
256 ftBGA (17x17 mm)
484 fpBGA (23x23 mm)
672 fpBGA (27x27 mm)
1156 fpBGA (35x35 mm)
ECP3-17
17
38
700
36
24
1
2/2
4 / 133
4 / 222
ECP3-35
33
72
1327
68
64
1
4/2
4 / 133
4 / 295
4 / 310
ECP3-70
67
240
4420
145
128
3
10 / 2
ECP3-95
92
240
4420
188
128
3
10 / 2
ECP3-150
149
372
6850
303
320
4
10 / 2
Packages and SERDES Channels/ I/O Combinations
4 / 295
8 / 380
12 / 490
4 / 295
8 / 380
12 / 490
8 / 380
16 / 586
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1021
Introduction_01.3
Lattice Semiconductor
Introduction
LatticeECP3 Family Data Sheet
Introduction
The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high perfor-
mance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous
interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture
and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.
The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to
486 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel
I/O standards.
The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices
utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib-
uted and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source
synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and
dual-boot capabilities.
The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad
range of interface standards, including DDR3, XGMII and 7:1 LVDS.
The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler-
ance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular
data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-empha-
sis and Receive Equalization settings make the SERDES suitable for transmission and reception over various
forms of media.
The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capa-
bility, bit-stream encryption, and TransFR field upgrade features.
The ispLEVER
®
design tool suite from Lattice allows large complex designs to be efficiently implemented using the
LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic synthesis tools.
The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
and route the design in the LatticeECP3 device. The ispLEVER tool extracts the timing from the routing and back-
annotates it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP3
family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the
unique aspects of their design, increasing their productivity.
1-2
LatticeECP3 Family Data Sheet
Architecture
March 2010
Preliminary Data Sheet DS1021
Architecture Overview
Each LatticeECP3 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys-
DSP™ Digital Signal Processing slices, as shown in Figure 2-1. In addition, the LatticeECP3 family contains
SERDES Quads on the bottom of the device.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit
without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF
block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for
flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-
dimensional array. Only one type of block is used per row.
The LatticeECP3 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated
18Kbit fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or
ROM. In addition, LatticeECP3 devices contain up to two rows of DSP slices. Each DSP slice has multipliers and
adder/accumulators, which are the building blocks for complex signal processing capabilities.
The LatticeECP3 devices feature up to 16 embedded 3.2Gbps SERDES (Serializer / Deserializer) channels. Each
SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each
group of four SERDES channels, along with its Physical Coding Sub-layer (PCS) block, creates a quad. The func-
tionality of the SERDES/PCS quads can be controlled by memory cells set during device configuration or by regis-
ters that are addressable during device operation. The registers in every quad can be programmed via the
SERDES Client Interface (SCI). These quads (up to four) are located at the bottom of the devices.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the
LatticeECP3 devices are arranged in seven banks, allowing the implementation of a wide variety of I/O standards.
In addition, a separate I/O bank is provided for the programming interfaces. 50% of the PIO pairs on the left and
right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engi-
neered support to aid in the implementation of high speed source synchronous standards such as XGMII, 7:1
LVDS, along with memory interfaces including DDR3.
Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP3 architecture provides two
Delay Locked Loops (DLLs) and up to ten Phase Locked Loops (PLLs). In addition, each LatticeECP3 family mem-
ber provides two DLLs per device. The PLL and DLL blocks are located at the end of the EBR/DSP rows.
The configuration block that supports features such as configuration bit-stream decryption, transparent updates
and dual-boot support is located toward the center of this EBR row. Every device in the LatticeECP3 family sup-
ports a sysCONFIG™ port located in the corner between banks one and two, which allows for serial or parallel
device configuration.
In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error
detect capability. The LatticeECP3 devices use 1.2V as their core voltage.
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1021
Architecture_01.5
Lattice Semiconductor
Architecture
LatticeECP3 Family Data Sheet
Figure 2-1. Simplified Block Diagram, LatticeECP3-35 Device (Top Level)
sysIO
Bank 0
sysIO
Bank 1
Configuration Logic:
Dual-boot, Encryption
and Transparent Updates
JTAG
On-chip Oscillator
sysIO
Bank
7
Enhanced DSP
Slices:
Multiply,
Accumulate and ALU
sysIO
Bank
2
Pre-engineered Source
Synchronous Support:
DDR3 - 800Mbps
Generic - Up to 1Gbps
sysCLOCK
PLLs & DLLs:
Frequency Synthesis
and Clock Alignment
Flexible sysIO:
LVCMOS, HSTL,
SSTL, LVDS
Up to 486 I/Os
sysMEM Block
RAM:
18Kbit
Flexible Routing:
Optimized for speed
and routability
Programmable
Function Units:
Up to 149K LUTs
sysIO Bank 6
SERDES/PCS SERDES/PCS
CH 3
CH 2
SERDES/PCS SERDES/PCS
CH 1
CH 0
sysIO Bank 3
3.2Gbps SERDES
Note: There is no Bank 4 or Bank 5 in LatticeECP3 devices.
PFU Blocks
The core of the LatticeECP3 device consists of PFU blocks, which are provided in two forms, the PFU and PFF.
The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF
blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain-
der of this data sheet will use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices numbered 0-3 as shown in Figure 2-2. Each slice contains
two LUTs. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs
associated with each PFU block.
2-2
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