74LV4020
14-stage binary ripple counter
Rev. 01 — 29 November 2005
Product data sheet
1. General description
The 74LV4020 is a low-voltage Si-gate CMOS device and is pin and function compatible
with the 74HC4020 and 74HCT4020.
The 74LV4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and 12 fully buffered parallel outputs (Q0, and
Q3 to Q13).
The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all
counter stages and forces all outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
2. Features
s
Optimized for low-voltage applications: 1.0 V to 5.5 V
s
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
s
Typical LOW-level output voltage (peak) or output ground bounce: V
OL(p)
< 0.8 V at
V
CC
= 3.3 V and T
amb
= 25
°C
s
Typical HIGH-level output voltage (valley) or output V
OH
undershoot: V
OH(v)
> 2 V at
V
CC
= 3.3 V and T
amb
= 25
°C
s
ESD protection:
x
HBM EIA/JESD22-A114-C exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C.
3. Applications
s
Frequency dividing circuits
s
Time delay circuits
s
Control counters
Philips Semiconductors
74LV4020
14-stage binary ripple counter
4. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 2.5 ns.
Symbol Parameter
t
PHL
,
t
PLH
propagation delay
CP to Q0
Qn to Q(n+1)
t
PHL
f
max
C
i
C
PD
[1]
Conditions
C
L
= 15 pF; V
CC
= 3.3 V
Min
-
-
Typ
12
7
16
100
3.5
20
Max
-
-
-
-
-
-
Unit
ns
ns
ns
MHz
pF
pF
propagation delay
MR to Qn
maximum input clock
frequency
input capacitance
power dissipation
capacitance
C
L
= 15 pF; V
CC
= 3.3 V
-
C
L
= 15 pF; V
CC
= 3.3 V
-
-
per gate; V
I
= GND to
V
CC
[1]
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
5. Ordering information
Table 2:
Ordering information
Package
Temperature range
74LV4020N
74LV4020D
74LV4020DB
74LV4020PW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
Type number
74LV4020_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 29 November 2005
2 of 20
Philips Semiconductors
74LV4020
14-stage binary ripple counter
6. Functional diagram
CP
MR
10
11
T
14-STAGE COUNTER
C
D
9
7
5
4
6
13
12
14
15
1
2
3
Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13
001aad722
Fig 1. Functional diagram
CTR14
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
9
7
5
4
6
13
12
14
15
1
2
3
10
11
+
CT
0
9
7
5
4
6
13
12
14
15
1
2
3
10
CP
CT
11
MR
13
001aad723
001aad724
Fig 2. Logic symbol
Fig 3. IEC logic symbol
CP
FF
T 0
Q
FF
T 1
Q
FF
T 2
Q
FF
T 3
Q
FF
T 4
Q
FF
T 5
Q
FF
T 6
Q
Q
RD
MR
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
Q0
Q3
Q4
Q5
Q6
FF
T 7
Q
FF
T 8
Q
FF
T 9
Q
FF
T 10
Q
FF
T 11
Q
FF
T 12
Q
FF
T 13
Q
Q
RD
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
Q7
Q8
Q9
Q10
Q11
Q12
Q13
001aad725
Fig 4. Logic diagram
74LV4020_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 29 November 2005
3 of 20
Philips Semiconductors
74LV4020
14-stage binary ripple counter
7. Pinning information
7.1 Pinning
Q11
Q12
Q13
Q5
Q4
Q6
Q3
GND
1
2
3
4
16 V
CC
15 Q10
14 Q9
13 Q7
4020
5
6
7
8
001aad721
12 Q8
11 MR
10 CP
9
Q0
Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16
7.2 Pin description
Table 3:
Symbol
Q11
Q12
Q13
Q5
Q4
Q6
Q3
GND
Q0
CP
MR
Q8
Q7
Q9
Q10
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
parallel output 11
parallel output 12
parallel output 13
parallel output 5
parallel output 4
parallel output 6
parallel output 3
ground (0 V)
parallel output 0
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
parallel output 8
parallel output 7
parallel output 9
parallel output 10
supply voltage
74LV4020_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 29 November 2005
4 of 20
Philips Semiconductors
74LV4020
14-stage binary ripple counter
8. Functional description
8.1 Function table
Table 4:
Input
CP
↑
↓
X
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑
= LOW-to-HIGH clock transition;
↓
= HIGH-to-LOW clock transition.
Function table
[1]
Output
MR
L
L
H
Q0, Q3 to Q13
no change
count
L
8.1.1 Timing diagram
1
CP input
MR input
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
001aad726
2
4
8
16
32
64
128
256
512 1024 2048 4096 8192 16384
Fig 6. Timing diagram
74LV4020_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 29 November 2005
5 of 20
PCB Design
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