74LV4020D datasheet, PDF - EEWORLD Datasheet

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74LV4020D: DescriptionCounter ICs 3.3V 14-STAGE BIN RIPPLE COUNT; Categorylogic logic; File Size100KB，21 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LV4020D Overview

Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT

74LV4020D Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SOIC
package instruction	SOP, SOP16,.25
Contacts	16
Reach Compliance Code	unknown
Other features	OUTPUTS FROM 12 STAGES AVAILABLE
Counting direction	UP
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	9.9 mm
Load capacitance (CL)	50 pF
Load/preset input	NO
Logic integrated circuit type	BINARY COUNTER
Maximum Frequency@Nom-Sup	20000000 Hz
MaximumI(ol)	0.006 A
Operating mode	ASYNCHRONOUS
Humidity sensitivity level	1
Number of digits	14
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
propagation delay (tpd)	54 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	NEGATIVE EDGE
width	3.9 mm
minfmax	36 MHz
Base Number Matches	1

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74LV4020

14-stage binary ripple counter

Rev. 01 — 29 November 2005

Product data sheet

1. General description

The 74LV4020 is a low-voltage Si-gate CMOS device and is pin and function compatible

with the 74HC4020 and 74HCT4020.

The 74LV4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and 12 fully buffered parallel outputs (Q0, and

Q3 to Q13).

The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all

counter stages and forces all outputs LOW, independent of the state of CP.

Each counter stage is a static toggle ﬂip-ﬂop.

2. Features

Optimized for low-voltage applications: 1.0 V to 5.5 V

Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

Typical LOW-level output voltage (peak) or output ground bounce: V

OL(p)

< 0.8 V at

= 3.3 V and T

amb

= 25

°C

Typical HIGH-level output voltage (valley) or output V

undershoot: V

OH(v)

> 2 V at

= 3.3 V and T

amb

= 25

°C

ESD protection:

HBM EIA/JESD22-A114-C exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

Multiple package options

Speciﬁed from

−40 °C

to +80

°C

and from

−40 °C

to +125

°C.

3. Applications

Frequency dividing circuits

Time delay circuits

Control counters

74LV4020D Related Products

	74LV4020D	74LV4020DB-T	74LV4020D-T	74LV4020N	74LV4020PW	74LV4020DB
Description	Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT	Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT	Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT	Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT	Counter ICs 14ST BIN RIP COUNTER	Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT
Maker	NXP	NXP	NXP	NXP	NXP	NXP
Parts packaging code	SOIC	SSOP	SOIC	DIP	TSSOP	SSOP
package instruction	SOP, SOP16,.25	SSOP,	SOP,	DIP, DIP16,.3	TSSOP, TSSOP16,.25	SSOP, SSOP16,.3
Contacts	16	16	16	16	16	16
Reach Compliance Code	unknown	unknown	unknown	unknown	compliant	compliant
Base Number Matches	1	1	1	1	1	1
Is it Rohs certified?	conform to	-	-	conform to	conform to	conform to
Other features	OUTPUTS FROM 12 STAGES AVAILABLE	OUTPUTS FROM 12 STAGES AVAILABLE	OUTPUTS FROM 12 STAGES AVAILABLE	OUTPUTS FROM 12 STAGES AVAILABLE	-	OUTPUTS FROM 12 STAGES AVAILABLE
Counting direction	UP	UP	UP	UP	-	UP
series	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	-	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDIP-T16	-	R-PDSO-G16
JESD-609 code	e4	e4	-	e4	-	e4
length	9.9 mm	6.2 mm	9.9 mm	19.025 mm	-	6.2 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	-	50 pF
Load/preset input	NO	YES	YES	NO	-	NO
Logic integrated circuit type	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	-	BINARY COUNTER
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	-	ASYNCHRONOUS
Number of digits	14	14	14	14	-	14
Number of functions	1	1	1	1	-	1
Number of terminals	16	16	16	16	-	16
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	-	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	SOP	SSOP	SOP	DIP	-	SSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	IN-LINE	-	SMALL OUTLINE, SHRINK PITCH
propagation delay (tpd)	54 ns	54 ns	54 ns	54 ns	-	54 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified
Maximum seat height	1.75 mm	2 mm	1.75 mm	4.2 mm	-	2 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	-	5.5 V
Minimum supply voltage (Vsup)	1 V	1 V	1 V	1 V	-	1 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	-	3.3 V
surface mount	YES	YES	YES	NO	-	YES
technology	CMOS	CMOS	CMOS	CMOS	-	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	-	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD	-	NICKEL PALLADIUM GOLD	-	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING	GULL WING	THROUGH-HOLE	-	GULL WING
Terminal pitch	1.27 mm	0.65 mm	1.27 mm	2.54 mm	-	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	-	DUAL
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	-	NEGATIVE EDGE
width	3.9 mm	5.3 mm	3.9 mm	7.62 mm	-	5.3 mm
minfmax	36 MHz	36 MHz	36 MHz	36 MHz	-	36 MHz

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