INTEGRATED CIRCUITS
CBTD16210
20-bit level shifting bus switch
with 10-bit output enables
Product specification
Supersedes data of 2000 Sep 25
2000 Oct 12
Philips
Semiconductors
Philips Semiconductors
Product specification
20-bit level shifting bus switch
with 10-bit output enables
CBTD16210
FEATURES
•
5Ω switch connection between two ports
•
TTL compatible control input levels
•
Designed to be used in 5.5 V to 3.3 V level shifting applications
•
Package options include shrink small outline (SSOP) and thin
shrink small outline (TSSOP)
DESCRIPTION
The CBTD16210 provides 20 bits of high-speed TTL-compatible bus
switching. The low on-state resistance of the switch allows
connections to be made with minimal propagation delay.
A diode to V
CC
is integrated in the circuit to allow for level shifting
between 5 V inputs and 3.3 V outputs.
The device is organized as a dual 10-bit bus switch with separate
output-enable (OE) inputs. It can be used as two 10-bit bus switches
or as one 20-bit bus switch. When OE is low, the associated 10-bit
bus switch is on, and port A is connected to port B. When OE is
high, the switch is open, and a high-impedance state exists between
the ports.
The CBTD16210 is characterized for operation from –40°C to
+85°C.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
An to Yn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled; V
O
= 0V or V
CC
Outputs disabled; V
CC
= 5.5V
TYPICAL
0.25
4.3
6.9
4.0
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
ORDER CODE
CBTD16210 DL
CBTD16210 DGG
DWG NUMBER
SOT370-1
SOT362-1
LOGIC SYMBOL
2
1A1
46
1B1
FUNCTION TABLE
INPUTS
1OE
L
2OE
L
H
L
H
OUTPUTS
1A, 1B
1A = 1B
1A = 1B
Z
Z
2A, 2B
2A = 2B
Z
2A = 2B
Z
12
1A10
36
1B10
L
H
H
88
1OE
13
2A1
35
2B1
H = High voltage level
L = Low voltage level
Z = High impedance “off ” state
24
2A10
25
2B10
47
2OE
SA00545
2000 Oct 12
2
853-2221 24787
Philips Semiconductors
Product specification
20-bit level shifting bus switch
with 10-bit output enables
CBTD16210
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NC
1OE, 2OE
1A1-1A10
1B1-1B10
2A1-2A10
2B1-2B10
GND
V
CC
NAME AND FUNCTION
No internal connection
Output enables
Inputs
Outputs
Inputs
Outputs
Ground (0V)
Positive supply voltage
1
48, 47
2, 3, 4, 5, 6, 7, 9, 10,
11, 12
46, 45, 44, 43, 42, 40,
39, 38, 37, 36
13, 14, 16, 18, 19, 20,
21, 22, 23, 24
35, 34, 33, 31, 30, 29,
28, 27, 26, 25
8, 17, 32, 41
15
NC
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1
2
3
4
5
6
7
8
9
48 1OE
47 2OE
46 1B1
45 1B2
44 1B3
43 1B4
42 1B5
41 GND
40 1B6
39 1B7
38 1B8
37 1B9
36 1B10
35 2B1
34 2B2
33 2B3
32 GND
31 2B4
30 2B5
29 2B6
28 2B7
27 2B8
26 2B9
25 2B10
1A8 10
1A9 11
1A10 12
2A1 13
2A2 14
V
CC
15
2A3 16
GND
17
2A4 18
2A5 19
2A6 20
2A7 21
2A8 22
2A9 23
2A10 24
SA00546
2000 Oct 12
3
Philips Semiconductors
Product specification
20-bit level shifting bus switch
with 10-bit output enables
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output voltage
3
DC output current
Storage temperature range
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
CBTD16210
RATING
–0.5 to +7.0
–50
–0.5 to +7.0
–0.5 to +5.5
128
–65 to +150
UNIT
V
mA
V
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
T
amb
DC supply voltage
High-level input voltage
Low-level Input voltage
Operating free-air temperature range
–40
PARAMETER
Min
4.5
2.0
0.8
+85
Max
5.5
UNIT
V
V
V
°C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= –40°C to +85°C
Min
V
IK
V
OH
I
I
I
CC
∆I
CC
C
I
C
IO(OFF)
r
on3
Input clamp voltage
Output high pass voltage
Input leakage current
Quiescent supply current
2
Additional supply current per
input pin
2
Control pins
Power-off leakage current
V
CC
= 4.5 V; I
I
= –18 mA
See Figure 1, page 6
V
CC
= 0 V; V
I
= 5.5 V
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 5.5 V; I
O
= 0, V
I
= V
CC
or GND;
1OE=2OE=GND
V
CC
= 5.5 V, one input at 3.4 V,
other inputs at V
CC
or GND
V
I
= 3 V or 0
V
O
= 3 V or 0, OE = V
CC
V
CC
= 4.5 V; V
1
= 0 V; I
I
= 64 mA
V
CC
= 4.5 V; V
1
= 0 V; I
I
= 30 mA
V
CC
= 4.5 V; V
1
= 2.4 V; I
I
= –15 mA
4.5
8
5
5
16
7
7
50
Ω
10
±1
1.5
2.5
Typ
1
Max
–1.2
V
V
µA
mA
mA
pF
pF
UNIT
NOTES:
1. All typical values are at V
CC
= 5 V, T
amb
= 25°C
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND
3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch.
On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
2000 Oct 12
4
Philips Semiconductors
Product specification
20-bit level shifting bus switch
with 10-bit output enables
CBTD16210
AC CHARACTERISTICS
GND = 0 V; t
R;
C
L
= 50 pF
SYMBOL
t
pd
t
PZH
t
PHZ
t
PZL
t
PLZ
PARAMETER DESCRIPTION
Propagation delay
1
Output enable time to HIGH level
Output disable time from HIGH level
Output enable time to LOW level
Output disable time from LOW level
1.5
1.0
1.5
1.5
5.0
2.5
6.0
3.5
LIMITS
–40°C to +85°C V
CC
= 5 V
±
0.5 V
Min
Mean
Max
250
7.5
4.5
9.0
6.0
ps
ns
ns
ns
ns
UNITS
NOTES:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
AC WAVEFORMS
V
M
= 1.5 V, V
IN
= GND to 3.0 V
3V
1.5V
INPUT
0V
t
PLH
t
PHL
V
OH
1.5V
OUTPUT
V
OL
1.5V
1.5V
TEST CIRCUIT AND WAVEFORMS
7V
From Output
Under Test
C
L
= 50 pF
500
Ω
S1
Open
GND
500
Ω
Load Circuit
TEST
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
open
7V
open
SA00028
Waveform 1. Input (An) to Output (Yn) Propagation Delays
DEFINITIONS
Load capacitance includes jig and probe capacitance;
C
L
=
see AC CHARACTERISTICS for value.
3V
Output Control
(Low-level
enabling
t
PZL
Output
Waveform 1
S1 at 7 V
(see Note)
t
PZH
Output
Waveform 2
S1 at Open
(see Note)
1.5 V
1.5 V
0V
3.5V
1.5 V
t
PHZ
V
OH
– 0.3V
1.5 V
0V
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
SA00012
t
PLZ
V
OL
+ 0.3V
V
OL
V
OH
SA00029
Waveform 2. 3-State Output Enable and Disable Times
2000 Oct 12
5
京公网安备 11010802033920号
EEWORLD
