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85314AGI-11LF

Description
Clock Buffer Low Skew 1-to-5 Diff -to-2.5V/3.3V LVPECL
Categorysemiconductor    Analog mixed-signal IC   
File Size338KB,21 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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85314AGI-11LF Overview

Clock Buffer Low Skew 1-to-5 Diff -to-2.5V/3.3V LVPECL

85314AGI-11LF Parametric

Parameter NameAttribute value
Product CategoryClock Buffer
ManufacturerIDT (Integrated Device Technology, Inc.)
RoHSDetails
Number of Outputs5 Output
Propagation Delay - Max1.4 ns
Supply Voltage - Max3.8 V
Supply Voltage - Min2.375 V
Maximum Operating Temperature+ 85 C
Minimum Operating Temperature- 40 C
Mounting StyleSMD/SMT
Package / CaseTSSOP-20
PackagingTube
Height1 mm
Length6.5 mm
Operating Supply Current80 mA
Factory Pack Quantitywyaeaqewfctvctubcx74
Width4.4 mm
Unit Weight0.006737 oz
Low Skew, 1-to-5 Differential-to-2.5V, 3.3V
LVPECL Fanout Buffer
ICS85314I-11
DATA SHEET
General Description
The ICS85314I-11 is a low skew, high performance 1-to-5
Differential-to-2.5V, 3.3V LVPECL fanout buffer. The ICS85314I-11
has two selectable differential clock inputs. The CLK0, nCLK0 and
CLK1, nCLK1 pairs can accept most standard differential input
levels. The clock enable is internally synchronized to eliminate runt
clock pulses on the outputs during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS85314I-11 ideal for those applications demanding well defined
performance and repeatability.
Features
Five differential 2.5V/3.3V LVPECL outputs
Selectable differential CLKx, nCLKx inputs
CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following
differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 700MHz
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Propagation delay: 1.8ns (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
nCLK_EN
Pulldown
Pin Assignment
D
Q
CK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
nCLK_EN
V
CC
nCLK1
CLK1
RESERVED
nCLK0
CLK0
CLK_SEL
V
EE
CLK0
Pulldown
nCLK0
Pullup
CLK1
Pulldown
nCLK1
Pullup
0
Q0
nQ0
1
Q1
nQ1
Q2
ICS85314I-11
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
CLK_SEL
Pulldown
nQ2
Q3
nQ3
Q4
nQ4
ICS85314I-11
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
ICS85314AGI-11 REVISION F SEPTEMBER 16, 2013
1
©2013 Integrated Device Technology, Inc.
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