EPM7096LC68-15 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> EPM7096LC68-15

EPM7096LC68-15: DescriptionCPLD - Complex Programmable Logic Devices CPLD - MAX 7000 96 Macro 52 IOs; CategoryProgrammable logic devices Programmable logic; File Size462KB，66 Pages; ManufacturerAltera (Intel)

Download Datasheet Parametric Compare View All

EPM7096LC68-15 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	EPM7096LC68-15	-	-	View	Buy Now

EPM7096LC68-15 Overview

CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 96 Macro 52 IOs

EPM7096LC68-15 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	LCC
package instruction	QCCJ, LDCC68,1.0SQ
Contacts	68
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
maximum clock frequency	100 MHz
In-system programmable	NO
JESD-30 code	S-PQCC-J68
JESD-609 code	e0
JTAG BST	NO
length	24.2316 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	52
Number of macro cells	96
Number of terminals	68
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 52 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	220
power supply	3.3/5,5 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	24.2316 mm
Base Number Matches	1

Preview

Download Datasheet

View All

MAX 7000

Programmable Logic

Device Family

Data Sheet

September 2005, ver. 6.7

Features...

■

High-performance, EEPROM-based programmable logic devices

(PLDs) based on second-generation MAX

architecture

5.0-V in-system programmability (ISP) through the built-in

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in

MAX 7000S devices

– ISP circuitry compatible with IEEE Std. 1532

Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S

devices

Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S

devices with 128 or more macrocells

Complete EPLD family with logic densities ranging from 600 to

5,000 usable gates (see

Tables 1

and

5-ns pin-to-pin logic delays with up to 175.4-MHz counter

frequencies (including interconnect)

PCI-compliant devices available

For information on in-system programmable 3.3-V MAX 7000A or 2.5-V

MAX 7000B devices, see the

MAX 7000A Programmable Logic Device Family

Data Sheet

or the

MAX 7000B Programmable Logic Device Family Data

Sheet.

Table 1. MAX 7000 Device Features

Feature

Usable

gates

Macrocells

Logic array

blocks

Maximum

user I/O pins

(ns)

FSU

(ns)

CO1

(ns)

CNT

(MHz)

EPM7032

600

2.5

151.5

EPM7064

1,250

2.5

151.5

EPM7096

1,800

7.5

4.5

125.0

EPM7128E

2,500

128

100

7.5

4.5

125.0

EPM7160E

3,200

160

104

100.0

EPM7192E

3,750

192

124

90.9

EPM7256E

5,000

256

164

90.9

Altera Corporation

DS-MAX7000-6.7

EPM7096LC68-15 Related Products

	EPM7096LC68-15	EPM7096QC100-7
Description	CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 96 Macro 52 IOs	CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 96 Macro 76 IOs
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Parts packaging code	LCC	QFP
package instruction	QCCJ, LDCC68,1.0SQ	QFP, QFP100,.7X.9
Contacts	68	100
Reach Compliance Code	compliant	compliant
Other features	CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V	CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
maximum clock frequency	100 MHz	166.7 MHz
In-system programmable	NO	NO
JESD-30 code	S-PQCC-J68	R-PQFP-G100
JESD-609 code	e0	e0
JTAG BST	NO	NO
length	24.2316 mm	20 mm
Humidity sensitivity level	3	3
Number of I/O lines	52	76
Number of macro cells	96	96
Number of terminals	68	100
Maximum operating temperature	70 °C	70 °C
organize	0 DEDICATED INPUTS, 52 I/O	0 DEDICATED INPUTS, 76 I/O
Output function	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QFP
Encapsulate equivalent code	LDCC68,1.0SQ	QFP100,.7X.9
Package shape	SQUARE	RECTANGULAR
Package form	CHIP CARRIER	FLATPACK
Peak Reflow Temperature (Celsius)	220	220
power supply	3.3/5,5 V	3.3/5,5 V
Programmable logic type	EE PLD	EE PLD
propagation delay	15 ns	7.5 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	3.65 mm
Maximum supply voltage	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	J BEND	GULL WING
Terminal pitch	1.27 mm	0.65 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	30
width	24.2316 mm	14 mm

Recommended Resources

Ikalogic test and measurement product series, do you know it?

X and Y are 16 kinds of logical relationship circuits

500W light modulation circuit

Spike Peak Voltage Measurement Circuit

555 light control street light circuit

DC motor follow-up control circuit

TM1804 DEMO: It is better to have more LEDs for running water lamps to make them feel better, so I add another string to make a total of 14 LEDs. TM1804 can be directly cascaded for expansion. The MCU uses a 1T 51...; naga568 51mcu

Does the boost topology circuit limit the duty cycle?: The boost topology circuit has a duty cycle limit? But the buck circuit does not have to be limited?...; Aguilera Power technology

Op amp differential amplification problem: The above figure is: the circuit diagram of differential input ADC conversion after differential acquisition voltage amplification Vshunt is the normal voltage input, R1=R3 1K, R2=R4 5K, R6=R5 100Ω, V...; bigbat Analog electronics

Urgent! Problems encountered in debugging A4 LCD: Hello everyone, I am debugging the LCD driver of A4 (ARM11) and I have encountered some problems. I don't know how to solve them. Please give me some advice. 1 When adjusting the backlight, the bright...; laopo163 Embedded System

Please tell me where the problem lies in the circuit of this instrument amplifier: ...; fish001 Analog electronics

【Project Outsourcing】Audio and video compression recording board: Audio and video compression recorderProject budget:￥ 30,000~40,000 Development cycle: 60 days Project Category: Embedded Bidding requirements:Project tags:H.264 video compression MEPG4 audio compressi...; CSTO项目交易 Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components