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EPM7096QC100-7

Description
CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 96 Macro 76 IOs
CategoryProgrammable logic devices    Programmable logic   
File Size462KB,66 Pages
ManufacturerAltera (Intel)
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EPM7096QC100-7 Overview

CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 96 Macro 76 IOs

EPM7096QC100-7 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerAltera (Intel)
Parts packaging codeQFP
package instructionQFP, QFP100,.7X.9
Contacts100
Reach Compliance Codecompliant
Other featuresCONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
maximum clock frequency166.7 MHz
In-system programmableNO
JESD-30 codeR-PQFP-G100
JESD-609 codee0
JTAG BSTNO
length20 mm
Humidity sensitivity level3
Dedicated input times
Number of I/O lines76
Number of macro cells96
Number of terminals100
Maximum operating temperature70 °C
Minimum operating temperature
organize0 DEDICATED INPUTS, 76 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP100,.7X.9
Package shapeRECTANGULAR
Package formFLATPACK
Peak Reflow Temperature (Celsius)220
power supply3.3/5,5 V
Programmable logic typeEE PLD
propagation delay7.5 ns
Certification statusNot Qualified
Maximum seat height3.65 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
MAX 7000
®
Programmable Logic
Device Family
Data Sheet
September 2005, ver. 6.7
Features...
High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX
®
architecture
5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see
Tables 1
and
2)
5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
f
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the
MAX 7000A Programmable Logic Device Family
Data Sheet
or the
MAX 7000B Programmable Logic Device Family Data
Sheet.
Table 1. MAX 7000 Device Features
Feature
Usable
gates
Macrocells
Logic array
blocks
Maximum
user I/O pins
t
PD
(ns)
t
SU
(ns)
t
FSU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
EPM7032
600
32
2
36
6
5
2.5
4
151.5
EPM7064
1,250
64
4
68
6
5
2.5
4
151.5
EPM7096
1,800
96
6
76
7.5
6
3
4.5
125.0
EPM7128E
2,500
128
8
100
7.5
6
3
4.5
125.0
EPM7160E
3,200
160
10
104
10
7
3
5
100.0
EPM7192E
3,750
192
12
124
12
7
3
6
90.9
EPM7256E
5,000
256
16
164
12
7
3
6
90.9
Altera Corporation
DS-MAX7000-6.7
1

EPM7096QC100-7 Related Products

EPM7096QC100-7 EPM7096LC68-15
Description CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 96 Macro 76 IOs CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 96 Macro 52 IOs
Is it lead-free? Contains lead Contains lead
Is it Rohs certified? incompatible incompatible
Parts packaging code QFP LCC
package instruction QFP, QFP100,.7X.9 QCCJ, LDCC68,1.0SQ
Contacts 100 68
Reach Compliance Code compliant compliant
Other features CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
maximum clock frequency 166.7 MHz 100 MHz
In-system programmable NO NO
JESD-30 code R-PQFP-G100 S-PQCC-J68
JESD-609 code e0 e0
JTAG BST NO NO
length 20 mm 24.2316 mm
Humidity sensitivity level 3 3
Number of I/O lines 76 52
Number of macro cells 96 96
Number of terminals 100 68
Maximum operating temperature 70 °C 70 °C
organize 0 DEDICATED INPUTS, 76 I/O 0 DEDICATED INPUTS, 52 I/O
Output function MACROCELL MACROCELL
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code QFP QCCJ
Encapsulate equivalent code QFP100,.7X.9 LDCC68,1.0SQ
Package shape RECTANGULAR SQUARE
Package form FLATPACK CHIP CARRIER
Peak Reflow Temperature (Celsius) 220 220
power supply 3.3/5,5 V 3.3/5,5 V
Programmable logic type EE PLD EE PLD
propagation delay 7.5 ns 15 ns
Certification status Not Qualified Not Qualified
Maximum seat height 3.65 mm 5.08 mm
Maximum supply voltage 5.25 V 5.25 V
Minimum supply voltage 4.75 V 4.75 V
Nominal supply voltage 5 V 5 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form GULL WING J BEND
Terminal pitch 0.65 mm 1.27 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature 30 30
width 14 mm 24.2316 mm
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