Operating Temperature Range ......................... -40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
(Typical
Application Circuit,
V
AVDD
= V
DVDD
= V
HVIN
= +2.4V to +3.6V, f
RF
= 300MHz to 450MHz, T
A
= -40°C to +125°C, unless oth-
erwise noted. Typical values are at V
AVDD
= V
DVDD
= V
HVIN
= +3.0V, f
RF
= 434 MHz, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
GENERAL CHARACTERISTICS
Supply Voltage (5V)
Supply Voltage (3V)
HVIN
V
DD
AVDD and DVDD unconnected from HVIN,
but connected together
HVIN, AVDD, and DVDD connected to
power supply
Operating
T
A
< +85ºC
Polling duty cycle: 10%
duty cycle
DRX mode OFF current
Deep-sleep current
Operating
Supply Current
I
DD
T
A
< +105ºC
(Note 2)
Polling duty cycle: 10%
duty cycle
DRX mode OFF current
Deep-sleep current
Operating
T
A
< +125ºC
(Note 2)
Polling duty cycle: 10%
duty cycle
DRX mode OFF current
Deep-sleep current
Startup Time
t
ON
Time for final signal detection, does not
include baseband filter settling (Note 2)
200
4.5
2.4
5.0
3.0
7.0
705
5.0
1.1
5.5
3.6
8.4
855
14.2
7.1
8.5
865
15.5
13.4
8.6
900
44.1
36.4
250
µs
µA
mA
µA
mA
µA
V
V
mA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (DIO, ADATA, FDATA)
Output High Voltage
Output Low Voltage
DIGITAL INPUTS (CS,
DIO, SCLK)
Input High Threshold
Input Low Threshold
V
OH
V
OL
V
IH
V
IL
I
SOURCE
= 250µA (Note 2)
I
SINK
= 250µA (Note 2)
0.9 x
V
HVIN
.
0.1 x
V
HVIN
V
HVIN
- 0.15
0.15
V
V
V
V
www.maximintegrated.com
Maxim Integrated
│
2
MAX1471
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Electrical Characteristics (continued)
(Typical
Application Circuit,
V
AVDD
= V
DVDD
= V
HVIN
= +2.4V to +3.6V, f
RF
= 300MHz to 450MHz, T
A
= -40°C to +125°C, unless oth-
erwise noted. Typical values are at V
AVDD
= V
DVDD
= V
HVIN
= +3.0V, f
RF
= 434 MHz, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Input-High Leakage Current
Input-Low Leakage Current
Input Capacitance
VOLTAGE REGULATOR
Output Voltage
SYMBOL
I
IH
C
IN
V
REG
I
IL
(Note 2)
(Note 2)
(Note 2)
V
HVIN
= 5.0V, I
LOAD
= 7.0mA
3.0
CONDITIONS
MIN
TYP
MAX
-20
20
2.0
UNITS
µA
µA
pF
V
AC Electrical Characteristics
(Typical
Application Circuit,
V
AVDD
= V
DVDD
= V
HVIN
= +2.4V to +3.6V, f
RF
= 300MHz to 450MHz, T
A
= -40°C to +125°C, unless oth-
erwise noted. Typical values are at V
AVDD
= V
DVDD
= V
HVIN
= +3.0V, f
RF
= 434 MHz, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
GENERAL CHARACTERISTICS
Receiver Sensitivity
Maximum Receiver Input Power
Level
Receiver Input Frequency Range
Receiver Image Rejection
LNA/MIXER
(Note 4)
LNA Input Impedance
Voltage Conversion Gain (High-
Gain Mode)
Input-Referred 3rd-Order Intercept
Point (High-Gain Mode)
Voltage Conversion Gain (Low-
Gain Mode)
Input-Referred 3rd-Order Intercept
Point (Low-Gain Mode)
LO Signal Feedthrough to
Antenna
Mixer Output Impedance
IF
Input Impedance
Operating Frequency
3dB Bandwidth
FM DEMODULATOR
Demodulator Gain
G
FM
2.2
mV/kHz
Z
OUT_MIX
Z
IN_IF
f
IF
Z
IN_LNA
Normalized to 50Ω
f
RF
= 315MHz
f
RF
= 434MHz
1 - j4.7
1 - j3.4
47.5
-38
12.2
-5
-90
330
330
10.7
10
dB
dBm
dB
dBm
dBm
Ω
Ω
MHz
MHz
RF
IN
RF
MAX
f
RF
IR
300
(Note 3)
45
0.2% BER, 4kbps
Manchester Code, 280kHz
IF BW, 50Ω
ASK
FSK
-114
-108
0
450
dBm
dBm
MHz
dB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
www.maximintegrated.com
Maxim Integrated
│
3
MAX1471
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
AC Electrical Characteristics (continued)
(Typical
Application Circuit,
V
AVDD
= V
DVDD
= V
HVIN
= +2.4V to +3.6V, f
RF
= 300MHz to 450MHz, T
A
= -40°C to +125°C, unless oth-
erwise noted. Typical values are at V
AVDD
= V
DVDD
= V
HVIN
= +3.0V, f
RF
= 434 MHz, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
ANALOG BASEBAND
Maximum Data Filter Bandwidth
Maximum Data Slicer Bandwidth
Maximum Peak Detector
Bandwidth
Maximum Data Rate
CRYSTAL OSCILLATOR
Crystal Frequency
Frequency Pulling by V
DD
Crystal Load Capacitance
f
XTAL
9.04
3
3
t
SC
t
CSS
t
CSI
t
CS
t
DO
t
DS
t
DH
t
CH
t
CL
t
CSH
t
DV
t
TR
30
30
125
2.125
80
30
30
100
100
30
25
25
13.728
MHz
ppm/V
pF
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
BW
DS
BW
PD
Manchester coded
Nonreturn to zero (NRZ)
BW
DF
50
100
50
33
66
kHz
kHz
kHz
kbps
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INTERFACE TIMING
(see Figure 8)
Minimum SCLK Setup to Falling
Edge of
CS
Minimum
CS
Falling Edge to
SCLK Rising-Edge Setup Time
Minimum
CS
Idle Time
Minimum
CS
Period
Maximum SCLK Falling Edge to
Data Valid Delay
Minimum Data Valid to SCLK
Rising-Edge Setup Time
Minimum Data Valid to SCLK
Rising-Edge Hold Time
Minimum SCLK High Pulse Width
Minimum SCLK Low Pulse Width
Minimum
CS
Rising Edge to
SCLK Rising-Edge Hold Time
Maximum
CS
Falling Edge to
Output Enable Time
Maximum
CS
Rising Edge to
Output Disable Time
Note
Note
Note
Note
1:
2:
3:
4:
Production tested at T
A
= +85°C. Guaranteed by design and characterization over entire temperature range.
Guaranteed by design and characterization. Not production tested.
The oscillator register (0x3) is set to the nearest integer result of f
XTAL
/ 100kHz (see the
Oscillator Frequency Register
section).
Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 15nH inductive degenera-
tion from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from
the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF. The voltage conversion gain is mea-
sured with the LNA input matching inductor, the degeneration inductor, and the LNA/mixer resonator in place, and does not
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