MC14044BCPG datasheet, PDF - EEWORLD Datasheet

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MC14044BCPG: DescriptionLatches 3-18V Quad R-S; Categorylogic logic; File Size137KB，7 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn; Environmental Compliance

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MC14044BCPG Overview

Latches 3-18V Quad R-S

MC14044BCPG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	ON Semiconductor
Parts packaging code	DIP
package instruction	DIP, DIP16,.3
Contacts	16
Reach Compliance Code	unknown
Factory Lead Time	1 week
series	4000/14000/40000
JESD-30 code	R-PDIP-T16
JESD-609 code	e3
length	19.175 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	R-S LATCH
Number of digits	4
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
method of packing	RAIL
Peak Reflow Temperature (Celsius)	260
power supply	5/15 V
Prop。Delay @ Nom-Sup	350 ns
propagation delay (tpd)	350 ns
Certification status	Not Qualified
Maximum seat height	4.44 mm
Maximum supply voltage (Vsup)	18 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	LOW LEVEL
width	7.62 mm

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MC14043B, MC14044B

CMOS MSI

Quad R−S Latches

The MC14043B and MC14044B quad R−S latches are constructed

with MOS P−Channel and N−Channel enhancement mode devices in a

single monolithic structure. Each latch has an independent Q output

and set and reset inputs. The Q outputs are gated through three−state

buffers having a common enable input. The outputs are enabled with a

logical “1” or high on the enable input; a logical “0” or low

disconnects the latch from the Q outputs, resulting in an open circuit at

the Q outputs.

Features

http://onsemi.com

MARKING

DIAGRAMS

MC140xxBCP

AWLYYWWG

•

Double Diode Input Protection

•

Three−State Outputs with Common Enable

•

Outputs Capable of Driving Two Low−power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature

Range

•

Supply Voltage Range = 3.0 Vdc to 18 Vdc

•

These Devices are Pb−Free and are RoHS Compliant

•

NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

MAXIMUM RATINGS

(Voltages Referenced to V

)

Symbol

, V

out

, I

out

stg

Parameter

DC Supply Voltage Range

Input or Output Voltage Range

(DC or Transient)

Input or Output Current

(DC or Transient) per Pin

Power Dissipation, per Package

(Note 1)

Ambient Temperature Range

Storage Temperature Range

Lead Temperature

(8−Second Soldering)

Value

−0.5

to +18.0

−0.5

to V

+ 0.5

500

−55

to +125

−65

to +150

260

Unit

°C

WL, L

YY, Y

WW, W

PDIP−16

P SUFFIX

CASE 648

SOIC−16

D SUFFIX

CASE 751B

140xxBG

AWLYWW

SOEIAJ−16

F SUFFIX

CASE 966

= Specific Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Indicator

MC14043B

ALYWG

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, V

and V

out

should be constrained

to the range V

or V

out

)

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V

or V

). Unused outputs must be left open.

Semiconductor Components Industries, LLC, 2013

April, 2013

−

Rev. 9

Publication Order Number:

MC14043B/D

MC14044BCPG Related Products

	MC14044BCPG	MC14044BD
Description	Latches 3-18V Quad R-S	Latches 3-18V Quad R-S
Is it Rohs certified?	conform to	incompatible
Maker	ON Semiconductor	ON Semiconductor
Parts packaging code	DIP	SOIC
package instruction	DIP, DIP16,.3	SOP, SOP16,.25
Contacts	16	16
Reach Compliance Code	unknown	not_compliant
series	4000/14000/40000	4000/14000/40000
JESD-30 code	R-PDIP-T16	R-PDSO-G16
JESD-609 code	e3	e0
length	19.175 mm	9.9 mm
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	R-S LATCH	R-S LATCH
Number of digits	4	4
Number of functions	1	1
Number of terminals	16	16
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C
Output characteristics	3-STATE	3-STATE
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	SOP
Encapsulate equivalent code	DIP16,.3	SOP16,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	SMALL OUTLINE
method of packing	RAIL	RAIL
Peak Reflow Temperature (Celsius)	260	240
power supply	5/15 V	5/15 V
Prop。Delay @ Nom-Sup	350 ns	350 ns
propagation delay (tpd)	350 ns	350 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	4.44 mm	1.75 mm
Maximum supply voltage (Vsup)	18 V	18 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	NO	YES
technology	CMOS	CMOS
Temperature level	MILITARY	MILITARY
Terminal surface	Matte Tin (Sn) - annealed	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	GULL WING
Terminal pitch	2.54 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	30
Trigger type	LOW LEVEL	LOW LEVEL
width	7.62 mm	3.9 mm

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