Am29DS163D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
22326
Revision
A
Amendment
+1
Issue Date
November 8, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am29DS163D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
■
Multiple bank architectures
— Two devices available with different bank sizes (refer
to Table 3)
■
Secured Silicon (SecSi) Sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data.
—
Customer lockable:
Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed.
— 64 Kbyte sector size
■
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero
■
Package options
— 48-ball FBGA
■
Top or bottom boot block
■
Manufactured on 0.23 µm process technology
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
■
20 Year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
■
Data Management Software (DMS)
— AMD-supplied software manages data programming
and erasing, enabling EEPROM emulation
— Eases sector erase limitations
■
Supports Common Flash Memory Interface (CFI)
■
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in
same bank
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
■
Any combination of sectors can be erased
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to reading array data
■
WP#/ACC input pin
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect status
— Acceleration (ACC) function provides accelerated
program times
■
Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
PERFORMANCE CHARACTERISTICS
■
High performance
— Access time as fast 100 ns
— Program time: 13 µs/word typical utilizing Accelerate function
■
Ultra low power consumption (typical values)
— 1 mA active read current at 1 MHz
— 5 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
Minimum 1 million write cycles guaranteed per sector
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
22326
Rev:
A
Amendment/1
Issue Date:
November 8, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29DS163D family consists of 16 megabit, 1.8
volt-only flash memory devices, organized as 1,048,576
words of 16 bits each or 2,097,152 bytes of 8 bits each.
Word mode data appears on DQ0–DQ15; byte mode
data appears on DQ0–DQ7. The device is designed to
be programmed in-system with the standard 1.8 volt
V
CC
supply, and can also be programmed in standard
EPROM programmers.
The device is available with an access time of 100 and
120 ns. The devices are offered in an 48-ball FBGA
package. Standard control pins—chip enable (CE#),
write enable (WE#), and output enable (OE#)—control
normal read and write operations, and avoid bus con-
tention issues.
The device requires only a
single 1.8 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
removal of EEPROM devices. DMS also allows the
system software to be simplified, as it performs all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s a n a d va n ta g e c o m pa r e d t o s y s te m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and
software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
is completed, the device automatically returns to read-
ing array data.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This is achieved in-system or via programming
equipment.
The device offers two power-saving features. When
addresses are stable for a specified amount of time,
the device enters the
automatic sleep mode.
The
system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
simultaneously read from the other bank, with zero la-
tency. This releases the system from waiting for the
completion of program or erase operations.
Am29DS163D Features
The
Secured Silicon (SecSi) Sector
is an additional
64 Kbyte sector capable of being permanently locked
by AMD or customers. The
SecSi Sector Indicator
Bit
(DQ7) is permanently set to a 1 if the part is
fac-
tory locked,
and set to a 0 if
customer lockable.
This
way, customer lockable parts can never be used to re-
place a factory locked part.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, reading and writing like any
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
4
Am29DS163D
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29DS163D Device Bus Operations .............................10
Sector Erase Command Sequence ........................................ 25
Erase Suspend/Erase Resume Commands ........................... 26
Figure 4. Erase Operation.............................................................. 26
Table 14. Am29DS163D Command Definitions.............................. 27
Write Operation Status . . . . . . . . . . . . . . . . . . . . 28
DQ7: Data# Polling ................................................................. 28
Figure 5. Data# Polling Algorithm .................................................. 28
Word/Byte Configuration ........................................................ 10
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 11
Accelerated Program Operation ......................................................11
Autoselect Functions .......................................................................11
RY/BY#: Ready/Busy# ............................................................ 29
DQ6: Toggle Bit I .................................................................... 29
Figure 6. Toggle Bit Algorithm........................................................ 29
Simultaneous Read/Write Operations with Zero Latency ....... 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
Table 2. Am29DS163D Device Bank Divisions ...............................12
Table 3. Top Boot Sector Addresses (Am29DS16xDT) ..................13
SecSi Sector Addresses for Top Boot Devices.............................. 13
Table 5. Bottom Boot Sector Addresses (Am29DS16xDB) ............14
SecSi Sector Addresses for Bottom Boot Devices......................... 14
DQ2: Toggle Bit II ................................................................... 30
Reading Toggle Bits DQ6/DQ2 ............................................... 30
DQ5: Exceeded Timing Limits ................................................ 30
DQ3: Sector Erase Timer ....................................................... 30
Table 15. Write Operation Status ................................................... 31
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32
Figure 7. Maximum Negative Overshoot Waveform ...................... 32
Figure 8. Maximum Positive Overshoot Waveform....................... 32
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. I
CC1
Current vs. Time (Showing Active
and Automatic Sleep Currents) ...................................................... 34
Figure 10. Typical I
CC1
vs. Frequency ............................................ 34
Autoselect Mode ..................................................................... 15
Table 7. Am29DS163D Autoselect Codes (High Voltage Method) 15
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Test Setup.................................................................... 35
Table 16. Test Specifications ......................................................... 35
Figure 12. Input Waveforms and Measurement Levels ................. 35
Sector/Sector Block Protection and Unprotection .................. 16
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................16
Table 9. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................16
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 13. Read Operation Timings ............................................... 36
Figure 14. Reset Timings ............................................................... 37
Write Protect (WP#) ................................................................ 17
Temporary Sector/Sector Block Unprotect ............................. 17
Figure 1. Temporary Sector Unprotect Operation........................... 17
Figure 2. In-System Sector/Sector Block Protect
and Unprotect Algorithms................................................................ 18
Word/Byte Configuration (BYTE#) .......................................... 38
Figure 15. BYTE# Timings for Read Operations............................ 38
Figure 16. BYTE# Timings for Write Operations............................ 38
Erase and Program Operations .............................................. 39
Figure 17. Program Operation Timings..........................................
Figure 18. Accelerated Program Timing Diagram..........................
Figure 19. Chip/Sector Erase Operation Timings ..........................
Figure 20. Back-to-back Read/Write Cycle Timings ......................
Figure 21. Data# Polling Timings (During Embedded Algorithms).
Figure 22. Toggle Bit Timings (During Embedded Algorithms)......
Figure 23. DQ2 vs. DQ6.................................................................
40
40
41
42
42
43
43
SecSi (Secured Silicon) Sector Flash Memory Region .......... 19
Hardware Data Protection ...................................................... 19
Low VCC Write Inhibit .....................................................................20
Write Pulse “Glitch” Protection ........................................................20
Logical Inhibit ..................................................................................20
Power-Up Write Inhibit ....................................................................20
Common Flash Memory Interface (CFI) . . . . . . . 20
Table 10. CFI Query Identification String ........................................ 20
System Interface String................................................................... 21
Table 12. Device Geometry Definition ............................................ 21
Table 13. Primary Vendor-Specific Extended Query ...................... 22
Temporary Sector/Sector Block Unprotect ............................. 44
Figure 24. Temporary Sector/Sector Block
Unprotect Timing Diagram ............................................................. 44
Figure 25. Sector/Sector Block Protect/Unprotect Timing Diagram 45
Alternate CE# Controlled Erase and Program Operations ..... 46
Figure 26. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 47
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data ................................................................ 23
Reset Command ..................................................................... 23
Autoselect Command Sequence ............................................ 23
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 24
Byte/Word Program Command Sequence ............................. 24
Unlock Bypass Command Sequence ..............................................24
Figure 3. Program Operation .......................................................... 25
Chip Erase Command Sequence ........................................... 25
Erase And Programming Performance . . . . . . . 48
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 48
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
6 x 8 mm package ................................................................. 49
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 50
Am29DS163D
5
DSP and ARM Processors
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