below which the device will not enter secondary breakdown.
Collector load lines for specific circuits must fall within the
applicable Safe Area to avoid causing a catastrophic failure.
To insure operation below the maximum T
J
,
power−temperature derating must be observed for both
steady state and pulse power conditions.
0.3
0.2
0.1
50
70 100
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 1. Active Region Safe Operating Area
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2
BD179G
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
1.0
0.8
I
C
= 0.1 A
0.25 A
0.5 A
1.0 A
0.6
T
J
= 25°C
0.4
0.2
0
0.2
0.3
0.5
1.0
2.0
3.0
5.0
10
I
B
, BASE CURRENT (mA)
20
30
50
100
200
Figure 2. Collector Saturation Region
hFE, DC CURRENT GAIN (NORMALIZED)
1000
700
500
300
200
100
70
50
30
20
10
2.0 3.0 5.0
T
J
= + 150°C
T
J
= + 25°C
T
J
= + 55°C
1.5
V
CE
= 2.0 V
1.2
VOLTAGE (VOLTS)
T
J
= 25°C
0.9
V
BE(sat)
@ I
C
/I
B
= 10
0.6
V
BE
@ V
CE
= 2.0 V
0.3
V
CE(sat)
@ I
C
/I
B
= 10
0
2.0 3.0 5.0
10
20 30
50
100
200 300 500 1000 2000
10
I
C
, COLLECTOR CURRENT (mA)
20 30 50 100 200 300 500 1000 2000
I
C
, COLLECTOR CURRENT (mA)
Figure 3. Current Gain
Figure 4. “On” Voltages
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1.0
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.01
0.01
D = 0.5
D = 0.2
D = 0.1
D = 0.05
D = 0.01
SINGLE PULSE
q
JC
(t) = r(t)
q
JC
q
JC
= 4.16°C/W MAX
q
JC
= 3.5°C/W TYP
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
- T
C
= P
(pk)
q
JC
(t)
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1.0
2.0 3.0
5.0
10
20
30
50
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
100
200 300
500
1000
t, TIME or PULSE WIDTH (ms)
Figure 5. Thermal Response
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3
BD179G
PACKAGE DIMENSIONS
TO−225
CASE 77−09
ISSUE AB
E
A1
Q
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. NUMBER AND SHAPE OF LUGS OPTIONAL.
DIM
A
A1
b
b2
c
D
E
e
L
L1
P
Q
MILLIMETERS
MIN
MAX
2.40
3.00
1.00
1.50
0.60
0.90
0.51
0.88
0.39
0.63
10.60
11.10
7.40
7.80
2.04
2.54
14.50
16.63
1.27
2.54
2.90
3.30
3.80
4.20
P
1
2
3
D
L1
L
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. BASE
2X
b2
2X
e
b
c
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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