®
HSP50210
Data Sheet
July 2, 2008
FN3652.5
Digital Costas Loop
The Digital Costas Loop (DCL) performs many of the
baseband processing tasks required for the demodulation of
BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM
waveforms. These tasks include matched filtering, carrier
tracking, symbol synchronization, AGC, and soft decision
slicing. The DCL is designed for use with the HSP50110
Digital Quadrature Tuner to provide a two chip solution for
digital down conversion and demodulation.
The DCL processes the In-phase (I) and Quadrature (Q)
components of a baseband signal which have been digitized
to 10 bits. As shown in the block diagram, the main signal
path consists of a complex multiplier, selectable matched
filters, gain multipliers, cartesian-to-polar converter, and soft
decision slicer. The complex multiplier mixes the I and Q
inputs with the output of a quadrature NCO. Following the
mix function, selectable matched filters are provided, which
perform integrate and dump or root raised cosine filtering
(α ~ 0.40). The matched filter output is routed to the slicer,
which generates 3-bit soft decisions, and to the cartesian-to-
polar converter, which generates the magnitude and phase
terms required by the AGC and Carrier Tracking Loops.
The PLL system solution is completed by the HSP50210
error detectors and second order Loop Filters that provide
carrier tracking and symbol synchronization signals. In
applications where the DCL is used with the HSP50110,
these control loops are closed through a serial interface
between the two parts. To maintain the demodulator
performance with varying signal power and SNR, an internal
AGC loop is provided to establish an optimal signal level at
the input to the slicer and to the cartesian-to-polar converter.
Features
• Clock Rates Up to 52MHz
• Selectable Matched Filtering with Root Raised Cosine or
Integrate and Dump Filter
• Second Order Carrier and Symbol Tracking Loop Filters
• Automatic Gain Control (AGC)
• Discriminator for FM/FSK Detection and Discriminator
Aided Acquisition
• Swept Acquisition with Programmable Limits
• Lock Detector
• Data Quality and Signal Level Measurements
• Cartesian-to-Polar Converter
• 8-Bit Microprocessor Control - Status Interface
• Designed to Work With the HSP50110 Digital Quadrature
Tuner
• 84 Lead PLCC
• Pb-Free Available (RoHS compliant)
Applications
• Satellite Receivers and Modems
• BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM
Demodulators
• Digital Carrier Tracking
• Related Products: HSP50110 Digital Quadrature Tuner,
D/A Converters HI5721, HI5731, HI5741
• HSP50110/210EVAL Digital Demod Evaluation Board
Block Diagram
CARRIER
TRACK
CONTROL
HI/LO
(COF)
LEVEL
DETECT
10
CARRIER ACQ/TRK
LOOP FILTER
NCO
COS SIN
I
RRC
FILTER
RRC
FILTER
INTEGRATE/
DUMP
INTEGRATE/
DUMP
SYMBOL
PHASE
ERROR
DETECT
8
CARTESIAN
TO
POLAR
8 MAGNITUDE
8
SLICER
PHASE
3
3
Q
I
LOOP
FILTER
CARRIER PHASE
ERROR DETECT
LEVEL
DETECT
LOCK
DETECT
LKINT
THRESH
A
OUT(9-0)
10
I SER OR
I
IN
(9-0)
SERCLK
OR CLK
Q SER OR
Q
IN
(9-0)
SYMBOL
TRACK
CONTROL
CONTROL/
STATUS
BUS
(SOF)
10
Q
8
DATA PATH MULTIPLEXER
10
B
OUT(9-0)
SMBLCLK
OEA
OEB
SYMBOL
TRACKING
LOOP FILTER
13
CONTROL
INTERFACE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HSP50210
Pin Description
NAME
VCC
GND
IIN9-0
QIN9-0
SYNC
COF
TYPE
-
-
I
I
I
O
+5V Power Supply.
Ground.
In-Phase Parallel Input. Data may be two’s complement or offset binary format (see Table 15). These inputs are
sampled by CLK when the SYNC signal is active Low. IIN9 is the MSB. See “Input Controller” on page 6.
Quadrature Parallel Input. Data may be two’s complement or offset binary format (see Table 15). These inputs are
sampled by CLK when the SYNC signal is active Low. QIN9 is the MSB. “Input Controller” on page 6.
Data Sync. When SYNC is asserted “Low”, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the
rising edge of CLK.
Carrier Offset Frequency. The frequency term generated by the Carrier Tracking Loop Filter is output serially via this
pin. The new offset frequency is shifted out MSB first by CLK or SLOCLK starting with the clock cycle after the
assertion of COFSYNC.
Carrier Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial data
word. (Programmable Polarity, see Table 42 on page 42, Bit 11).
Sampler Offset Frequency. Sample frequency correction term generated by the Symbol Tracking Loop Filter is
output serially via this pin. The frequency word is shifted out MSB first by CLK or SLOCLK starting with the clock
cycle after assertion of SOFSYNC.
Sampler Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial data
word. (Programmable Polarity, see Table 42 on page 42, Bit 12).
Address Bus. The address on these pins specify a target register for reading or writing (see “Microprocessor
Interface” on page 27). A0 is the LSB.
Microprocessor Interface Data Bus. This bi-directional bus is used for reading and writing to the processor interface.
These are the data I/O pins for the processor interface. C0 is the LSB.
Write. This is the write strobe for the processor interface (see “Microprocessor Interface” on page 27).
Read. This is the read enable for the processor interface (see “Microprocessor Interface” on page 27).
Freeze Symbol Tracking Loop. Asserting this pin “high” zeroes the sampling error into the Symbol Tracking Loop
Filter (see “Symbol Tracking Loop Filter” on page 17).
Freeze Carrier Tracking Loop. Asserting this pin “high” zeroes the carrier Phase Error input to the Carrier Tracking
Loop Filter.
Lock Detect Interrupt. This pin is asserted “high” for at least 4 CLK cycles when the Lock Detector Integration cycle
is finished (see “Lock Detector” on page 23). Used as an interrupt for a processor. The Lock Detect Interrupt may
be asserted “high” longer than 4 CLK cycles, depending on the Lock Detector mode.
Threshold Exceeded. This output is asserted “low” when the magnitude out of the Cartesian to Polar converter
exceeds the programmable Power Detect Threshold (see Table 16 on page 33 and “AGC” on page 10).
Slow Clock. Optional serial clock used for outputting data from the Carrier and Symbol Tracking Loop Filters. The
clock is programmable and has a 50% duty cycle. Note: Not used when the HSP50110 is used with the HSP50210
(see Table 42 page 42).
In-Phase Serial Input. Serial data input for In-Phase Data. Data on this pin is shifted in MSB first and is synchronous
to SERCLK (see “Input Controller” on page 6).
Quadrature Serial Input. Serial data input for Quadrature Data. Data on this pin is shifted in MSB first and is
synchronous to SERCLK (see “Input Controller” on page 6).
Serial Word Sync. This input is asserted “high” one CLK before the first data bit of the serial word (see Figure 2).
Serial Clock. May be asynchronous to other clocks. Used to clock in serial data (see “Input Controller” on page 6).
A Output. Data on this output depend on the configuration of Output Selector. AOUT9 is the MSB (see Table 43 on
page 44).
B Output. Data on this output depend on the configuration of Output Selector. BOUT9 is the MSB (see Table 43 page 44).
Symbol Clock. 50% duty cycle clock aligned with soft bit decisions (see Figure 19).
DESCRIPTION
COFSYNC
SOF
O
O
SOFSYNC
A2-0
C7-0
WR
RD
FZ_ST
FZ_CT
LKINT
O
I
I/O
I
I
I
I
O
THRESH
SLOCLK
O
O
ISER
QSER
SSYNC
SERCLK
AOUT9-0
BOUT9-0
SMBLCLK
I
I
I
I
O
O
O
3
FN3652.5
July 2, 2008
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