Da ta She et, V2. 2, Aug . 2 00 1
C167CS-4R
C167CS-L
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2001-08
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 2001.
All Rights Reserved.
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circuits, descriptions and charts stated herein.
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Da ta She et, V2. 2, Aug . 2 00 1
C167CS-4R
C167CS-L
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
C167CS
Revision History:
Previous Version:
2001-08
2000-12
2000-06
1999-06
1999-03
V2.1 (Intermediate version)
V2.0
(Advance Information)
V2.2
Page
4
25, 27
50ff
52f
54
57
59
60
76
Page
All
2
52
53
56
60f
64
65
70
71
72
75
1)
Subjects (major changes from V2.1, 2000-12 to V2.2, 2001-08)
Figure 2
corrected (pins 98, 99)
Figure 5
and
Figure 6
updated
Output voltage/current specification improved
Limit values for
I
IDO
and
I
PDR
increased due to the usage of a standard
oscillator
Figure 10
corrected
Figure 12
updated for 40 MHz
Clock parameters adjusted
TUE note includes P1H
Package drawing updated
1)
Subjects (major changes from V2.0, 2000-06 to V2.1, 2000-12)
Maximum operating frequency updated to 40 MHz
Derivative table updated
RSTIN level for
I
DD
corrected to
V
IL
(was
V
IL2
)
Current unit corrected to
µ
A
Input clock range adjusted
Note 5 detailed
Parameters
tc
10
,
tc
12
,
tc
13
,
tc
14
,
tc
15
,
tc
16
,
tc
17
,
tc
18
,
tc
19
changed
Relative bus timing parameters added
Parameter
tc
25
changed, notes adapted
Notes adapted
Parameter
tc
28
changed
Parameters
t
42
,
t
43
,
t
44
,
t
46
,
t
47
changed
New package due to new assembly line. MQFP-144-1 for current deliveries only, will be discontinued.
Controller Area Network (CAN): License of Robert Bosch GmbH
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16-Bit Single-Chip Microcontroller
C166 Family
C167CS-4R, C167CS-L
C167CS
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80/60/50 ns Instruction Cycle Time at 25/33/40 MHz CPU Clock
– 400/303/250 ns Multiplication (16
×
16 bit), 800/606/500 ns Division (32-/16-bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30/25 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
• On-Chip Memory Modules
– 3 KBytes On-Chip Internal RAM (IRAM)
– 8 KBytes On-Chip Extension RAM (XRAM)
– 32 KBytes On-Chip Program Mask ROM
• On-Chip Peripheral Modules
– 24-Channel 10-bit A/D Converter with Programmable Conversion Time
down to 7.8
µ
s
– Two 16-Channel Capture/Compare Units
– 4-Channel PWM Unit
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
– Two On-Chip CAN Interfaces (Rev. 2.0B active) with 2
×
15 Message Objects
(Full CAN/Basic CAN), can work on one bus with 30 objects
– On-Chip Real Time Clock
• Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 111 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
Data Sheet
1
V2.2, 2001-08
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