MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P−channel
and N−channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
Features
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•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
Capable of Driving Two Low−Power TTL Loads or One
•
•
•
•
•
Low−Power Schottky TTL Load Over the Rated Temperature
Range
Triple Diode Protection on All Inputs
Pin−for−Pin Replacement for CD4069UB
Meets JEDEC UB Specifications
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
SOIC−14
D SUFFIX
CASE 751A
SOEIAJ−14
F SUFFIX
CASE 965
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
IN 1
OUT 1
IN 2
OUT 2
IN 3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
IN 6
OUT 6
IN 5
OUT 5
IN 4
OUT 4
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±10
500
−55 to +125
−65 to +150
260
Unit
V
V
OUT 3
V
SS
MARKING DIAGRAMS
mA
14
mW
°C
°C
°C
14
14
069U
ALYWG
G
1
TSSOP−14
A
WL, L
YY, Y
WW, W
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
14069UG
AWLYWW
1
SOIC−14
1
SOEIAJ−14
14
MC14069UB
ALYWG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 11
Publication Order Number:
MC14069UB/D
MC14069UB
1
3
5
9
11
13
2
4
6
8
10
12
V
DD
= PIN 14
V
SS
= PIN 7
INPUT*
V
DD
OUTPUT
V
SS
*Double diode protection on all inputs not shown
(1/6 of circuit shown)
Figure 1. Logic Diagram
Figure 2. Circuit Schematic
V
DD
14 OUTPUT
INPUT
7
V
SS
C
L
20 ns
90%
50%
10%
20 ns
V
DD
V
SS
V
OH
V
OL
t
TLH
PULSE
GENERATOR
INPUT
t
PHL
OUTPUT
t
PLH
90%
50%
10%
t
THL
Figure 3. Switching Time Test Circuit and Waveforms
ORDERING INFORMATION
Device
MC14069UBDG
NLV14069UBDG*
MC14069UBDR2G
NLV14069UBDR2G*
MC14069UBDTR2G
NLV14069UBDTR2G*
MC14069UBFELG
Package
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
SOEIAJ−14
(Pb−Free)
Shipping
†
55 Units / Rail
55 Units / Rail
2500 Units / Tape & Reel
2500 Units / Tape & Reel
2500 Units / Tape & Reel
2500 Units / Tape & Reel
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC14069UB
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
−55_C
Characteristic
Output Voltage
V
in
= V
DD
V
in
= 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
“1” Level
(V
O
= 0.5 Vdc)
(V
O
= 1.0 Vdc)
(V
O
= 1.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current (Notes 3 and 4)
(Dynamic plus Quiescent,
Per Gate) (C
L
= 50 pF)
Output Rise and Fall Times (Note 3)
(C
L
= 50 pF)
t
TLH
, t
THL
= (1.35 ns/pF) C
L
+ 33 ns
t
TLH
, t
THL
= (0.60 ns/pF) C
L
+ 20 ns
t
TLH
, t
THL
= (0.40 ns/pF) C
L
+ 20 ns
Propagation Delay Times (Note 3)
(C
L
= 50 pF)
t
PLH
, t
PHL
= (0.90 ns/pF) C
L
+ 20 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C
L
+ 22 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C
L
+ 17 ns
I
OH
Source
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
5.0
10
15
−
−
−
−
−
−
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
−
−
−
−
−
−
−
±0.1
−
0.25
0.5
1.0
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±0.00001
5.0
0.0005
0.0010
0.0015
−
−
−
−
−
−
−
±0.1
7.5
0.25
0.5
1.0
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
−
−
−
−
−
−
−
±1.0
−
7.5
15
30
mAdc
V
IH
5.0
10
15
4.0
8.0
12.5
−
−
−
4.0
8.0
12.5
2.75
5.50
8.25
−
−
−
4.0
8.0
12.5
−
−
−
mAdc
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.0
2.0
2.5
Min
−
−
−
4.95
9.95
14.95
−
−
−
25_C
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
Max
0.05
0.05
0.05
−
−
−
1.0
2.0
2.5
125_C
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.0
2.0
2.5
Vdc
Unit
Vdc
“1” Level
V
OH
Vdc
Input Voltage
(V
O
= 4.5 Vdc)
(V
O
= 9.0 Vdc)
(V
O
= 13.5 Vdc)
“0” Level
V
IL
Vdc
Sink
I
in
C
in
I
DD
mAdc
pF
mAdc
I
T
I
T
= (0.3
mA/kHz)
f + I
DD
/6
I
T
= (0.6
mA/kHz)
f + I
DD
/6
I
T
= (0.9
mA/kHz)
f + I
DD
/6
−
−
−
100
50
40
200
100
80
−
−
−
−
−
−
mAdc
t
TLH
,
t
THL
ns
t
PLH
,
t
PHL
5.0
10
15
−
−
−
−
−
−
−
−
−
65
40
30
125
75
55
−
−
−
−
−
−
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in
mA
(per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.002.
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3
MC14069UB
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
14
A
B
8
A3
H
1
7
E
L
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
_
7
_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0
_
7
_
0.25
M
B
M
13X
b
0.25
M
C A
A
S
B
S
X 45
_
h
DETAIL A
e
A1
C
SEATING
PLANE
M
SOLDERING FOOTPRINT*
6.50
1
14X
1.18
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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4
MC14069UB
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X
K
REF
0.10 (0.004)
0.15 (0.006) T U
S
M
T U
S
V
S
N
2X
L/2
14
8
0.25 (0.010)
M
L
PIN 1
IDENT.
1
7
B
−U−
N
F
DETAIL E
K
K1
J J1
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0
_
8
_
0
_
8
_
SECTION N−N
−W−
C
0.10 (0.004)
−T−
SEATING
PLANE
D
G
H
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT*
7.06
1
14X
0.36
14X
1.26
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
0.65
PITCH
DIMENSIONS: MILLIMETERS
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