DS1045
4-Bit Dual Programmable Delay Line
www.maxim-ic.com
FEATURES
All-silicon time delay
Two programmable outputs from a single
input produce output-to-output delays
between 9ns and 84ns depending on device
type
Programmable via four input pins
Programmable increments of 3ns to 5ns with
a minimum of 9ns and a maximum of 84ns
Output pulse is a reproduction of input pulse
after
Delay with both leading and trailing edge
accuracy
Standard 16-pin DIP or surface mount 16-pin
SOIC
Auto-insertable
Low-power CMOS design is TTL-compatible
PIN ASSIGNMENT
IN
V
CC
EA
A0
A1
A2
A3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
EB
OUTB
B0
B1
B2
B3
OUTA
IN
V
CC
EA
A0
A1
A2
A3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
EB
OUTB
B0
B1
B2
B3
OUTA
DS1045 16-Pin DIP
See Mech. Drawings
Section
DS1045S 16-Pin SOIC (300-mil)
See Mech. Drawings
Section
PIN DESCRIPTION
IN
OUTA, OUTB
A0-A3
B0-B3
EA
,
EB
V
CC
GND
- Delay Line Input
- Delay Line Outputs
- Parallel Program Inputs
for OUT1
- Parallel Program Inputs
for OUT2
- Enable A and B Inputs
- +5V Input
- Ground
DESCRIPTION
The DS1045 is a programmable silicon delay line having one input and two 4-bit programmable delay
outputs. Each 4-bit programmable output offers the user 16 possible delay values to select from, starting
with a minimum inherent DS1045 delay of 9ns and a maximum achievable delay in the standard DS1045
family of 84ns. The standard DS1045 product line provides the user with three devices having uniform
delay increments of 3ns, 4ns, and 5ns, depending on the device. Table 1 presents standard device family
and delay capability. Additionally, custom delay increments are available for special order through Dallas
Semiconductor.
The DS1045 is TTL and CMOS-compatible and capable of driving ten 74LS-type loads. The output
produced by the DS1045 is both rising and falling edge precise. The DS1045 programmable silicon delay
line has been designed as a reliable, economic alternative to hybrid programmable delay lines. It is
offered in a standard 16-pin auto-insertable DIP and a space-saving surface mount 16-pin SOIC package.
1 of 6
04/26/04
DS1045
PARALLEL PROGRAMMING
Parallel programming of the DS1045 is accomplished via the set of parallel inputs A0-A3 and B0-B3 as
shown in Figure 1. Parallel input A0-A3 and B0-B3 accept TTL levels and are used to set the delay
values of outputs OUTA and OUTB, respectively. Sixteen possible delay values between the minimum
9ns delay and the maximum delay of the DS1045-x device version can be selected using the parallel
programming inputs A0-A3 or B0-B3 (see Table 2, “Delay vs. Programmed Input”). For example, the
DS1045-3 outputs OUTA or OUTB and can be programmed to produce 16 possible delays between the
9ns (minimum) and the 54ns (maximum) in 3ns increment levels.
For applications that do not require frequent reprogramming, the parallel inputs can be set using fixed
logic levels, as would be produced by jumpers, DIP switches, or TTL levels as produced by computer
systems. Maximum flexibility in parallel programming can be achieved when inputs are set by computer-
generated data. By using the enable input pins for each respective programmed output and observing the
input setup (t
DSE
) and hold time (t
DHE
) requirements, data can be latched on an 8-bit bus. If the enable
pins,
EA
and
EB
, are not used to latch data, they should be set to a logic level 1. After each change in the
programmed delay value, a settling time (t
EDV
) or (t
PDV
) is required before the delayed output signal is
reliably produced. Since the DS1045 is a CMOS design, undefined input pins should be connected to well
defined logic levels and not left floating.
PART NUMBER TABLE
Table 1
PART NUMBER
DS1045-3
DS1045-4
DS1045-5
STEP ZERO DELAY
9
±=1ns
9
±=1ns
9
±=1ns
MAX DELAY TIME
54ns
69ns
84ns
MAX DELAY
TOLERANCE
±2.5ns
±3.3ns
±4.1ns
NOTE:
Additional delay step times are available from Dallas Semiconductor by special order. Consult factory for
availability.
BLOCK DIAGRAM
Figure 1
2 of 6
DS1045
DELAY VS. PROGRAMMED VALUE
Table 2
PART NUMBER
DS1045-3
DS1045-4
DS1045-5
A0 OR B0
A1 OR B1
A2 OR B2
A3 OR B3
OUTPUT DELAY VALUE
9 12 15 18 21 24 27 30 33 36 39 42
9 13 17 21 25 29 33 37 41 45 49 53
9 14 19 24 29 34 39 44 49 54 59 64
PROGRAM VALUES FOR EACH DELAY VALUE
0 1 0 1 0 1 0
1
0
1
0
1
0 0 1 1 0 0 1
1
0
0
1
1
0 0 0 0 1 1 1
1
0
0
0
0
0 0 0 0 0 0 0
0
1
1
1
1
45
57
69
0
0
1
1
48
61
74
1
0
1
1
51
65
79
0
1
1
1
54
69
84
1
1
1
1
DS1045 TEST CIRCUIT
Figure 2
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1045.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected to the output. The DS1045 parallel
inputs are controlled by an interface to a central computer. All measurements are fully automated with
each instrument controlled by the computer over an IEEE 488 bus.
3 of 6
DS1045
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
Short Circuit Output Current
-1.0V to +7.0V
0°C to 70°C
-55°C to +125°C
See J-STD-020A specification
50mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Logic 1
Input Logic 0
Input Leakage
Active Current
Logic 1 Output
Current
Logic 0 Output
Current
SYMBOL
V
CC
V
IH
V
IL
I
I
I
CC
I
OH
I
OL
0
≤V
I
≤V
CC
V
CC
=5.25V
PERIOD=1
µs
V
CC
= 4.75V V
OH
=
4.0V
V
CC
= 4.75V V
OL
=
0.5V
TEST CONDITION
MIN
4.75
2.2
-0.5
-1.0
TYP
5.0
MAX
5.25
V
CC
+0.5
0.8
+1.0
35.0
-1.0
8
(0°C to 70°C)
UNITS
V
V
µA
µA
mA
mA
mA
NOTES
1
1
1
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Period
Pulse Width
Input to Output Delay
Parallel Input Change to
Delay Invalid
Parallel Input Valid to Delay
Valid
Enable Width
Data Setup to Enable
Data Hold from Enable
Enable to Delay Invalid
Enable to Delay Valid
SYMBOL
t
PERIOD
t
WI
t
PLH
, t
PHL
t
PDX
t
PDV
t
EW
t
DSE
t
DHE
t
EDX
t
EDV
15
10
0
5
15
MIN
4 x t
WI
100% of
output
delay
0
10
TYP
(0°C to 70°C; V
CC
5V
±
5%)
MAX
UNITS
ns
ns
Table 1
ns
ns
ns
ns
ns
ns
ns
ns
2
NOTES
4 of 6
DS1045
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
C
IN
MIN
TYP
MAX
10
(T
A
= 25°C)
UNITS
pF
NOTES
T
A
=25°C
±=3°C
V
CC
= 5.0V
±=0.1V
Input Pulse = 3.0V high to 0.0V low
±=0.1V
Input Source Impedance = 50Ω maximum
Rise and fall times = 3.0ns max. between 0.6V and 2.4V
Pulse Width = 250ns
Period = 500ns
Output Load = 74F04
Measurement Point = 1.5V on inputs and outputs
Output Load Capacitance = 15pF
TEST CONDITIONS
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE,
EA
,
EB
= V
IH
TIMING DIAGRAM: LATCHED PARALLEL MODE
5 of 6
京公网安备 11010802033920号
EEWORLD
