Datas heet
AS1 328
3A , 1. 5MHz Sy nch r on ou s DC / DC S tep -Do wn C o n v e r t e r
1 General description
The AS1328 is a high-efficiency, synchronous buck converter that
can deliver up to 3A. The device is available in adjustable- and fixed-
output voltage versions. The wide input voltage range (2.7V to 5.5V),
automatic Powersave Mode and minimal external component
requirements make the AS1328 perfect for any single Li-Ion battery-
powered application.
Typical quiescent current with no load is 25μA and decreases to
1μA
in shutdown mode. The highly efficient duty cycle (100%) pro-
vides low dropout operation, prolonging battery life in portable sys-
tems.
The AS1328 is available with user adjustable output voltage between
0.6V and V
IN
via an external resistor divider.
The switching frequency (1.5MHz) allows the use of a small surface
mount inductor.
A user adjustable Softstart function limits the input current during
start-up.
The AS1328 is available in a TQFN (3x3mm) 16-pin package.
AS1328 offers several power monitoring functions.
Part Name
AS1328A
AS1328B
AS1328C
Description
Power-Okay Function
Low Battery Detection
Power-Okay Function with 215ms delay
2 Key features
High Efficiency: up to 96%
Input Voltage Range: 2.7V to 5.5V
Output Voltage Range (factory set): 0.7V to 4.8V
User-Adjustable Output Voltage Range: 0.6V to V
IN
Output Current: 3A
Low battery detection or Power Okay function
Constant Frequency Operation (1.5MHz) or Powersave Opera-
tion
Softstart Function
No Schottky diode required
Automatic Powersave Operation
Low Dropout Operation: 100% Duty Cycle
215ms POK timeout (optional)
Low Quiescent Supply Current: 25μA
Shutdown Current:
1μA
Thermal protection
TQFN (3x3mm) 16-pin Package.
3 Applications
The device is ideal for mobile communication devices, laptops and
PDAs, SSD, point of load supply of
μP
and FPGA based systems,
medical instruments or any other application with high current
requirements.
Figure 1. AS1328 - Typical application diagram
2.2μH
C
IN
44μF
VIN
SRC
EN
POK
GND
MODE
SW
PGND
C
OUT
44μF
V
IN
2.7V to 5.5V
V
OUT
0.7V to 4.8V, 3A
AS1328A
GND
FB
RSI
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Revision 1.04
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AS1328
Datasheet - P i n a s s i g n m e n t
4 Pin assignment
Figure 2. Pin assignment (top view) of the two versions AS1328A (POK function) and AS1328B (LBI function)
PVDD
PVDD
VDD
SRC
VDD
15
16
15
14
13
16
14
PVDD
SW
SW
PGND
1
2
3
4
5
12
GND
EN
POK
RSI
PVDD
SW
SW
PGND
13
SRC
12
FB
FB
1
2
3
4
5
GND
EN
LBO
LBI
AS1328A
Exposed Pad
6
7
8
11
10
9
AS1328B
Exposed Pad
6
7
11
10
9
PGND
MODE
PGND
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Revision 1.04
MODE
GND
GND
GND
GND
8
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AS1328
Datasheet - P i n a s s i g n m e n t
4.1 Pin description
Table 1. Pin description
Pin Number
1, 16
15
Pin Name
PVDD
VDD
Description
Power Supply Voltage. Supply Voltage for the power output stage. This pin must be closely decoupled to
PGND with a > 2x22μF ceramic capacitor.
Supply Voltage. Supply Voltage for the DC-DC core: possibly a RC filter can be inserted from PVDD to VDD
to improve switching noise rejection.
Active-High Enable Input. Pulling this pin to logic high enables the device, a logic low level puts the device
in shutdown mode. In shutdown mode all functions are disabled, drawing supply current <1μA. EN voltage is
preferably referred to VDD and GND pins instead of PVDD and PGND.
Note:
This pin should not be left floating.
Reset Input for POK. This input resets the 215ms timer of the POK signal.
As long as RSI is low the POK signal is low if the nominal output voltage is out of range. A high
input to RSI will reset the 215ms POK timer (where available) and delay the signal as long as
RSI stays high. A RSI high-to-low transition restarts the 215ms counter as long as the output
voltage is within regulation.
Note:
Do not leave this pin floating.
LBI
AS1328B
Low Battery Comparator Input. Input of a 1.2V threshold comparator. Connect it to GND if
not used. The voltage at this pin must be referred to GND.
Power-OK Output. Open Drain Output. Leave this pin unconnected if the Power-OK feature is
not used. Otherwise use an external pull-up resistor.
Logic low: out of regulation;
logic high: within regulation.
The POK signal reacts after a 215ms delay (POK_d) or no delay. Both variants (POK and
POK_d) are available.
Low Battery Comparator Output. Open Drain Output. Leave this pin unconnected if the LBO
feature is not used. Otherwise use an external pull-up resistor. This output is low when the
voltage on LBI is less than 1.2V. The logic level is not valid in shutdown and during startup.
11
EN
RSI
9
AS1328A
POK
10
AS1328A
LBO
AS1328B
14
FB
Feedback Pin. Feedback input to the error amplifier. For the factory set output voltage connect this pin
directly to V
OUT
. For the user adjustable out put voltage connect a resistor divider tap to this pin. Connect the
ground terminal of the resistor divider to GND and not to PGND. The output voltage can be adjusted from
0.6V to V
IN
by: V
OUT
= 0.6V[1 + (R
1
/R
2
)]
A capacitor should be connected in parallel to R1 to ensure stability and improved load transient response.
Analog Ground. GND and PGND should have only one point connection.
Power Ground. Connect all grounds to this pin.
Switch Node Connection to Inductor. These pins must be shorted together on the PCB to connect one
terminal of the external inductor to the drains of the internal synchronous power MOSFET switches.
Mode Pin. Logic-controlled mode input for automatic Powersave Operation of the regulator.
High: automatic Powersave Operation;
Low: fixed frequency operation.
Slew Rate Control. This pin controls the soft start function of the AS1328. If not used, leave this pin floating
or connect it to V
DD
in case of a noisy environment.
For a user defined start-up time, connect a ceramic capacitor C
SS
from SRC to GND. The capacitor will be
charged with 4μA nominal current. Alternatively, the SRC pin can also be forced by a voltage source.
Exposed Pad. The exposed pad must be connected to PGND. Ensure a good connection to the PCB to
achieve an optimal thermal performance.
6, 7, 12
4, 5
2, 3
8
GND
PGND
SW
MODE
13
SRC
Exposed Pad
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Revision 1.04
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AS1328
Datasheet - A b s o l u t e m a x i m u m r a t i n g s
5 Absolute maximum ratings
Stresses beyond those listed in
Table 2
may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in
Section 6 Electrical characteristics on page 5
is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Electrical Parameters
V
IN
to GND
SW to GND
EN, FB to GND
P-Channel Switch Source Current (DC)
N-Channel Switch Source Current (DC)
Peak SW Sink and Source Current
Input Current (latch-up immunity)
Electrostatic Discharge
Electrostatic Discharge HBM
Temperature Ranges and Storage Conditions
Thermal Resistance
JA
Junction Temperature
Storage Temperature Range
-55
36.7
+125
+150
ºC/W
ºC
ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with IPC/
JEDEC J-STD-020“Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State Surface
Mount Devices”.
Represents an unlimited floor life time
on PCB
1.5
kV
Norm: MIL 883 E method 3015
-100
-0.3
7
V
V
V
A
A
A
mA
Norm: JEDEC 78
-0.3(DC)
V
IN
+ 0.3 (DC)
-1.5 (100ns) V
IN
+1 (100ns)
-0.3
V
IN
4
4
6
100
Min
Max
Units
Comments
Package Body Temperature
+260
5
1
85
ºC
Humidity non-condensing
Moisture Sensitive Level
%
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Revision 1.04
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AS1328
Datasheet - E l e c t r i c a l c h a r a c t e r i s t i c s
6 Electrical characteristics
V
IN
= EN = 5V (or V
IN
> V
OUT
+ 0.5V whatever is higher), C
IN
= C
OUT
= 2x22μF, L = 2.2μH (unless otherwise specified). Typical values are @
T
AMB
= +25ºC. All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical
Quality Control) methods.
Table 3. Electrical characteristics
Symbol
T
A
T
J
V
IN
Parameter
Operating Temperature Range
Operating Junction
Temperature Range
Input Voltage Range
Dropout Operation;
V
OUT
/V
IN
= 90%,
I
LOAD
= 0A
I
Q
Quiescent Supply Current
1
Conditions
Min
-40
-40
2.7
Typ
Max
+85
+125
5.5
Units
°C
°C
V
250
μA
25
Powersave Mode; MODE=high,
RSI=low,
V
OUT
= 105% x V
OUT(NOM)
,
I
LOAD
= 0A,
T
AMB
= +25ºC
3
MODE=high, RSI=high, V
EN
= 0V, V
IN
= 5.5V,
T
AMB
= +25ºC
I
OUT
I
SHDN
Regulation
V
OUT
A
CC
V
FB
I
FB
V
LNR
Output Current
Shutdown Current
A
0.1
1
μA
Regulated Output Voltage
Range
Regulated Output Voltage
Accuracy
Regulated Feedback Voltage
FB pin Current
V
IN
Line Regulation
Output Voltage
Load Regulation
Minimum on-pulse duration
Peak Inductor Current
3
2
User adjustable output version
Fixed output version,
DC average value,
I
LOAD
= 100mA
Only for User-Adjustable Output Voltage version
MODE=low,
V
IN
= 2.7V (or V
IN
> V
OUT
+ 0.5V whatever is
higher) to 5.5V,
I
LOAD
= 100mA
MODE=low,
I
LOAD
= 1μA to 3A
I
LOAD
= 1A
0.6
-1
0.59
-100
0.1
0.6
V
IN
+1
0.61
+100
V
%
V
nA
%/V
V
LOADREG
DC-DC switches
0.1
%/A
on
I
PK
R
PFET
R
NFET
100
3.5
4.5
35
35
ns
A
m
m
+1
μA
μA
P-Channel FET R
DS(ON)
N-Channel FET R
DS(ON)
V
EN
= 0V, V
SW
= 0V or 5V, V
IN
= 5V,
T
AMB
= +25ºC
V
EN
= 0V, V
SW
= 0V or 5V, V
IN
= 5V,
T
AMB
= +85ºC
1.2
-1
0.01
1
I
LSW
Switch Leakage Current
Control inputs
V
IH
V
IL
I
EN
Logic Input Threshold
EN Input Leakage Current
V
EN
= 0V to 5.5V, V
IN
= 5.5V
Revision 1.04
0.4
-0.1
0.01
+0.1
V
μA
5 - 30
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