NXP Semiconductors
Technical Data
Document Number: MC33889
Rev. 15.0, 8/2016
System basis chip (SBC) with low
speed fault tolerant CAN interface
The 33889 is an SBC having a fully protected, fixed 5.0 V low drop-out
regulator, with current limit, overtemperature prewarning and reset. An SBC
device is a monolithic IC combining many functions repeatedly found in
standard microcontroller-based systems, e.g., protection, diagnostics,
communication, power, etc.
An output drive with sense input is also provided to implement a second 5.0 V
regulator using an external PNP. The 33889 has Normal, Standby, Stop and
Sleep modes; an internally switched high-side power supply output with two
wake-up inputs; programmable timeout or window watchdog, Interrupt, Reset,
serial peripheral interface (SPI) input control, and a low-speed fault tolerant
CAN transceiver, compatible with CAN 2.0 A and B protocols for module-to-
module communications. The combination is an economical solution for power
management, high-speed communication, and control in MCU-based systems.
This device is powered by SMARTMOS technology.
Features
• VDD1: 5.0 V low drop voltage regulator, current limitation, overtemperature
detection, monitoring and reset function with total current capability 200 mA
• V2: tracking function of VDD1 regulator; control circuitry for external bipolar
ballast transistor for high flexibility in choice of peripheral voltage and current
supply
• Four operational modes
• Low standby current consumption in Stop and Sleep modes
• Built-in low speed 125 kbps fault tolerant CAN physical interface.
• External high voltage wake-up input, associated with HS1 V
BAT
switch
• 150 mA output current capability for HS1 V
BAT
switch allowing drive of
external switches pull-up resistors or relays
33889
SYSTEM BASIS CHIP
EG SUFFIX (PB-FREE)
PLASTIC PACKAGE
98ASB42345B
28-PIN SOICW
ORDERING INFORMATION
Device
(Add R2 Suffix for
Tape and Reel)
MC33889BPEG
*MC33889DPEG
Temperature
Range (T
A
)
-40 to 125 °C
Package
28 SOICW
*
Recommended for new designs
33889
5.0 V
VDD1
GND
VSUP
V2CTRL
V2
HS1
L0
L1
WDOG
RTH
CANH
CANL
RTL
VPWR
V2
MCU
CS
SCLK
MOSI
MISO
SPI
RST
INT
CS
SCLK
MOSI
MISO
TXD
RXD
Local Module Supply
Wake-Up Inputs
Safe Circuits
Twisted
Pair
CAN Bus
Figure 1. 33889 simplified application diagram
© 2016 NXP B.V.
1
Device variations
Table 1. Device variations between the 33889D and 33889B versions
(1)
Parameters
Symbol
Trait
Min.
Differential Receiver, Recessive To Dominant Threshold (By
Definition, V
DIFF
= V
CANH
-V
CANL
)
V
DIFF1
Typ
Max.
Min.
Differential Receiver, Dominant To Recessive Threshold (Bus
Failures 1, 2, 5)
V
DIFF2
Typ
Max.
Min.
CANH Output Current (V
CANH
= 0; TX = 0.0)
I
CANH
Typ
Max.
Min.
CANL Output Current (V
CANL
= 14 V; TX = 0.0)
Detection threshold for Short circuit to Battery voltage
loop time Tx to Rx, no bus failure, ISO configuration
loop time Tx to Rx, with bus failure, ISO configuration
loop time Tx to Rx, with bus failure and +-1.5V gnd shift,
5 node network, ISO configuration
Minimum Dominant time for Wake up on CANL or CANH (Tem
Vbat mode)
I
CANL
Vcanh
tLOOPRD
tLOOPRD-F
tLOOPRD/DR-F+GS
Min.
tWAKE
typ
Max.
T2SPI timing
Device behavior
CANH or CANL open wire recovery principle
Rx behavior in TermVbat mode
Reference
MC33889B on page 32
after 4 non consecutive
after 4 consecutive pulses
pulses
Rx recessive, dominant
pulse to signal bus traffic
T2spi
Min.
Typ
Max.
Max.
Max.
Max.
Device part number
MC33889B
(2)
3.2 V
2.6 V
2.1 V
3.2 V
2.6 V
2.1 V
50 mA
75 mA
110 mA
50 mA
90 mA
135 mA
Vsup/2 + 5V
N/A
N/A
N/A
N/A
30
N/A
not specified, 25us spec
applied
MC33889D
(2)
3.5 V
3.0 V
2.5 V
3.5 V
3.0 V
2.5 V
50 mA
100 mA
130 mA
50 mA
140 mA
170 mA
Vsup/2 + 4.55V
1.5us
1.9us
3.6us
8
16
30
25us
Reference
MC333889D on page 32
Rx recessive, no pulse
Notes
1. This datasheet uses the term 33889 in the inclusive sense, referring to both the D version (33889D) and the B version (33689B).
2. The 33889D and 33889B versions are nearly identical. However, where variations in characteristic occur, these items will be separated onto
individual lines.
33889
2
NXP Semiconductors
2
Internal block diagram
VSUP
Dual Voltage Regulator
VSUP Voltage Monitor
VDD1 Voltage Monitor
HS1 Control
Oscillator
V2CTRL
V2
VDD1
HS1
L0
L1
Programmable
Wake-Up Inputs
INT
Interrupt
Watchdog
Reset
Mode Control
TX
WDOG
RST
CS
SCLK
MOSI
MISO
GND
Figure 2. 33889 internal block diagram
RX
SPI
Interface
VSUP
V2
Fault Tolerant
CAN
Transceiver
RTH
CAN H
CAN L
RTL
33889
NXP Semiconductors
3
3
Pin connections
RX
TX
VDD1
RST
INT
GND
GND
GND
GND
V2CTRL
VSUP
HS1
L0
L1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WDOG
CS
MOSI
MISO
SCLK
GND
GND
GND
GND
CANL
CANH
RTL
RTH
V2
Figure 3. 33889 pin connections
A functional description of each pin can be found in the
Functional pin description
section page
20.
Table 2. Pin definitions
Pin
1
2
3
4
5
6 -9, 20 - 23
10
11
12
13 - 14
15
16
17
18
19
24
25
26
27
28
Pin name
RX
TX
VDD1
RST
INT
GND
V2CTRL
VSUP
HS1
L0, L1
V2
RTH
RTL
CANH
CANL
SCLK
MISO
MOSI
CS
WDOG
Pin function
Output
Input
Power Output
Output
Output
Ground
Output
Power Input
Output
Input
Input
Output
Output
Output
Output
Input
Output
Input
Input
Output
Formal Name
Receiver Data
Transmitter Data
Voltage Regulator One
Reset
Interrupt
Ground
Voltage Source 2 Control
Voltage Supply
High-Side Output
Level 0 - 1 Inputs
Voltage Regulator Two
RTH
RTL
CAN High
CAN Low
System Clock
Master In/Slave Out
Master Out/Slave In
Chip Select
Watchdog
CAN bus receive data output pin
CAN bus receive data input pin
5.0 V pin is a 2% low drop voltage regulator for to the microcontroller supply.
This is the device reset output pin whose main function is to reset the MCU.
This output is asserted LOW when an enabled interrupt condition occurs.
These device ground pins are internally connected to the package lead frame to
provide a 33889-to-PCB thermal path.
Output drive source for the V2 regulator connected to the external series pass
transistor.
Supply input pin.
Output of the internal high-side switch.
Inputs from external switches or from logic circuitry.
5.0 V pin is a low drop voltage regulator dedicated to the peripherals supply.
Pin for connection of the bus termination resistor to CANH.
Pin for connection of the bus termination resistor to CANL.
CAN high output pin.
CAN low output pin.
Clock input pin for the Serial Peripheral Interface (SPI).
SPI data sent to the MCU by the 33889. When CS
LOW
is HIGH, the pin is in the high
impedance state.
SPI data received by the 33889.
The CS
LOW
input pin is used with the SPI bus to select the 33889. When the CS
LOW
is asserted LOW, the 33889 is the selected device of the SPI bus.
The WDOG output pin is asserted LOW if the software watchdog is not correctly
triggered.
Definition
33889
4
NXP Semiconductors
4
4.1
Electrical characteristics
Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Electrical ratings
V
SUP
V
LOG
I
V
I
V
WU
I
WU
V
TRWU
V
2INT
V
BUS
V
CANH
/V
CANL
V
TR
V
RTL
, V
RTH
V
RTH
/V
RTL
Supply Voltage at VSUP
Continuous voltage
Transient voltage (Load dump)
Logic Signals (RX, TX, MOSI, MISO, CS, SCLK, RST, WDOG, INT)
Output current VDD1
HS1
Voltage
Output Current
L0, L1
DC Input voltage
DC Input current
Transient input voltage (according to ISO7637 specification) and with external
component per
Figure 4.
DC voltage at V2 (V2INT)
DC Voltage On Pins CANH, CANL
Transient Voltage At Pins CANH, CANL
0.0 < V2-INT < 5.5 V; VSUP = 0.0; T < 500 ms
Transient Voltage On Pins CANH, CANL
(Coupled Through 1.0 nF Capacitor)
DC Voltage On Pins RTH, RTL
Transient Voltage At Pins RTH, RTL
0.0 < V2-INT < 5.5 V; VSUP = 0.0; T < 500 ms
ESD voltage (HBM 100 pF, 1.5 k)
CANL, CANH, HS1, L0, L1
RTH, RTL
All other pins
ESD voltage (Machine Model) All pins, MC33889B
ESD voltage (CDM) All pins, MC33889D
Pins 1,14,15, & 28
All other pins
RTH, RTL Termination Resistance
-0.3 to 27
40
-0.3 to V
DD1
+0.3
Internally Limited
-0.2 to V
SUP
+0.3
Internally Limited
-0.3 to 40
-2.0 to 2.0
+-100
0 to 5.25
-20 to +27
-40 to +40
-150 to +100
-0.3 to +27
-0.3 to +40
±4.0
±3.0
±2.0
±200
750
500
500 to 16000
V
V
mA
V
A
V
mA
V
V
V
V
V
V
V
Ratings
Max.
Unit
Notes
V
ESDH
kV
(3)
V
ESD-MM
V
ESD-CDM
R
T
V
V
Ω
(3) (4)
(4)
33889
NXP Semiconductors
5
Embedded System
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