12:2, Differential-To-LVDS Multiplexer
ICS854S202I-01
DATASHEET
General Description
The ICS854S202I-01 is a 12:2 Differential-to-LVDS Clock Multiplexer
which can operate up to 3GHz. The ICS854S202I-01 has twelve se-
lectable differential clock inputs, any of which can be independently
routed to either of the two LVDS outputs. The CLKx, nCLKx input
pairs can accept LVPECL, LVDS or CML levels. The fully differential
architecture and low propagation delay make it ideal for use in clock
distribution circuits.
Features
• Two differential 2.5V LVDS clock outputs
• Twelve selectable differential clock inputs
• CLKx, nCLKx pairs can accept the following differential input levels:
LVPECL, LVDS, CML
• Maximum output frequency: 3GHz
• Propagation delay: 1.1ns (maximum)
• Input skew: 100ps (maximum)
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS (12kHz – 20MHz): 0.16ps (typical)
• Full 2.5V operating supply mode
• -40°C to 85°C ambient operating temperature
Block Diagram
nCLK1
CLK1
GND
nCLK0
CLK0
V
DD
OEB
CLK11
nCLK11
GND
CLK10
nCLK10
CLK2
nCLK2
SELA_0
SELA_1
V
DD
QA
nQA
GND
SELA_2
SELA_3
CLK3
nCLK3
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
48-Pin LQFP
5
32
6
7mm x 7mm x 1.4mm
31
7
30
package body
8
29
Y Package
9
28
Top View
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
SELA_[3:0]
Pulldown
CLK0
Pulldown
nCLK0
Pullup/Pulldown
CLK1
Pulldown
nCLK1
Pullup/Pulldown
CLK2
Pulldown
nCLK2
Pullup/Pulldown
CLK3
Pulldown
nCLK3
Pullup/Pulldown
CLK4
Pulldown
Pullup/Pulldown
4
ICS854S202I-01
QA
nQA
Pullup
OEA
nCLK4
CLK5
Pulldown
Pullup/Pulldown
nCLK5
CLK6
Pulldown
nCLK6
Pullup/Pulldown
CLK7
Pulldown
nCLK7
Pullup/Pulldown
CLK8
Pulldown
nCLK8
Pullup/Pulldown
CLK9
Pulldown
Pullup/Pulldown
nCLK9
CLK10
Pulldown
nCLK10
Pullup/Pulldown
CLK11
Pulldown
nCLK11
Pullup/Pulldown
SELB_[3:0]
Pulldown
4
Pullup
CLK9
nCLK9
SELB_0
SELB_1
V
DD
QB
nQB
GND
SELB_2
SELB_3
CLK8
nCLK8
QB
nQB
OEB
ICS854S202AYI-01 REV. A DECEMBER 18, 2012
1
nCLK4
CLK4
GND
nCLK5
CLK5
V
DD
OEA
CLK6
nCLK6
GND
CLK7
nCLK7
©2012 Integrated Device Technology, Inc.
ICS854S202I-01 Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3,
4,
9,
10
5, 18, 32, 43
6, 7
8, 15, 22, 29,
39, 46
11
12
13
14
16
17
18, 43
19
20
21
23
24
25
26
27,
28,
33,
34
30, 31
35
36
37
38
40
41
42
44
Name
CLK2
nCLK2
SELA_0,
SELA_1,
SELA_2,
SELA_3
V
DD
QA, nQA
GND
CLK3
nCLK3
nCLK4
CLK4
nCLK5
CLK5
V
DD
OEA
CLK6
nCLK6
CLK7
nCLK7
nCLK8
CLK8
SELB_3,
SELB_2,
SELB_1,
SELB_0
nQB, QB
nCLK9
CLK9
nCLK10
CLK10
nCLK11
CLK11
OEB
CLK0
Input
Input
Type
Pulldown
Pullup/Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Clock select pins for Bank A output pair. See Control Input Function
Table. LVCMOS/LVTTL interface levels. See Table 3B.
Power supply pins.
Clock outputs. LVDS interface levels.
Power supply ground.
Pulldown
Pullup/Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Positive supply pins.
Pullup
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pullup/Pulldown
Pulldown
Output enable pin. Controls enabling and disabling of QA, nQA
output pair. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Clock select pins for Bank B output pair. See Control Input Function
Table. LVCMOS/LVTTL interface levels. See Table 3C.
Clock outputs. LVDS interface levels.
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup
Pulldown
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Output enable pin. Controls enabling and disabling of QB, nQB
output pair. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Input
Pulldown
Power
Output
Power
Input
Input
Input
Input
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
Input
Pulldown
Output
Input
Input
Input
Input
Input
Input
Input
Input
ICS854S202AYI-01 REV. A DECEMBER 18, 2012
2
©2012 Integrated Device Technology, Inc.
ICS854S202I-01 Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Number
45
47
48
Name
nCLK0
CLK1
nCLK1
Input
Input
Input
Type
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Description
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Table 3A. OEA, OEB Control Input Function Table
Input
OEA, OEB
0
1
Output
QA, nQA, QB, nQB
Disabled (Logic LOW)
Active (default)
ICS854S202AYI-01 REV. A DECEMBER 18, 2012
3
©2012 Integrated Device Technology, Inc.
ICS854S202I-01 Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 3B. SEL_A Control Input Function Table
Control Input
Input Selected to QA, nQA
SELA_3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SELA_2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SELA_1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SELA_0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK0, nCLK0 (default)
CLK1, nCLK1
CLK2, nCLK2
CLK3, nCLK3
CLK4, nCLK4
CLK5, nCLK5
CLK6, nCLK6
CLK7, nCLK7
CLK8, nCLK8
CLK9, nCLK9
CLK10, nCLK10
CLK11, nCLK11
Output at logic LOW
Output at logic LOW
Output at logic LOW
Output at logic LOW
Table 3C. SEL_B Control Input Function Table
Control Input
Input Selected to QB, nQB
SELB_3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SELB_2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SELB_1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SELB_0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4
CLK0, nCLK0 (default)
CLK1, nCLK1
CLK2, nCLK2
CLK3, nCLK3
CLK4, nCLK4
CLK5, nCLK5
CLK6, nCLK6
CLK7, nCLK7
CLK8, nCLK8
CLK9, nCLK9
CLK10, nCLK10
CLK11, nCLK11
Output at logic LOW
Output at logic LOW
Output at logic LOW
Output at logic LOW
©2012 Integrated Device Technology, Inc.
ICS854S202AYI-01 REV. A DECEMBER 18, 2012
ICS854S202I-01 Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
Storage Temperature, T
STG
JA
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
70.2 C/W (0 mps)
-65 C to 150 C
Table 4A. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
110
Maximum
2.625
128
Units
V
ma
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High
Current
SELA_[3:0],
SELB_[3:0]
OEA, OEB
Input Low
Current
SELA_[3:0,
SELB_[3:0]
OEA, OEB
V
DD
= 2.625V
V
DD
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.625V, V
IN
= 0V
-10
-150
Test Conditions
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
150
10
Units
V
V
A
A
A
A
I
IL
Table 4C. Differential DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High
Current
Input Low
Current
CLK[0:11],
nCLK[0:11]
CLK[0:11]
nCLK[0:11]
Test Conditions
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.625V, V
IN
= 0V
-10
-150
0.15
GND + 0.5
1.5
V
DD
– 0.7
Minimum
Typical
Maximum
150
Units
A
A
A
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage:
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH.
ICS854S202AYI-01 REV. A DECEMBER 18, 2012
5
©2012 Integrated Device Technology, Inc.
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