Edition 2001-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
User Manual
C166S V2
Table of Contents
1
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6
1.2.7
1.2.8
1.2.9
1.2.10
2
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.3.1
2.3.3.2
2.3.4
2.3.5
2.3.6
2.3.6.1
2.3.6.2
2.4
2.4.1
2.4.2
2.4.3
2.4.3.1
2.4.3.2
2.5
2.5.1
2.5.2
2.5.2.1
2.5.2.2
2.5.2.3
2.5.2.4
2.5.3
2.5.4
Page
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Technical Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
On-Chip Memory Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Management Unit (DMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Program Memory Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interrupt and PEC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OCDS and JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
External Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
System Control Unit (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock Generation Unit (CGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
On-Chip Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Central Processing Unit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . . . .
Branch Target Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Branch Detection and Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . .
Sequential and Mispredicted Instruction Flow . . . . . . . . . . . . . . . . . . . .
Correctly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . . .
Incorrectly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . .
Atomic and Extend Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code Addressing via Code Segment and Instruction Pointer . . . . . . . .
IFU Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The CPU Configuration Register CPUCON1 . . . . . . . . . . . . . . . . . . .
The CPU Configuration Register CPUCON2 . . . . . . . . . . . . . . . . . . .
Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Mapped GPR Banks and the Global Register Bank . . . . . . . .
Local Register Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Context Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing the selected Physical Register Bank . . . . . . . . . . . . . . . . .
Context Switching of the Global Register Bank . . . . . . . . . . . . . . . . .
Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Long and Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing via Data Page Pointer DPP . . . . . . . . . . . . . . . . . . . . . .
DPP Override Mechanism in the C166S V2 CPU . . . . . . . . . . . . . . .
Long Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The CoREG Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
15
17
18
19
20
22
24
24
26
27
28
30
30
31
34
36
40
40
40
42
45
46
48
49
51
52
53
56
63
User Manual
V 1.7, 2001-01
Microchip MCU
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