NB3Nxxxxx - VCXO Series
3.3V PureEdge] VCXO
Clock Generator with
Differential LVPECL Outputs
Description
The NB3NXXXXX
−
series voltage−controlled crystal oscillator
(VCXO) devices are designed to meet today’s requirements for 3.3 V
LVPECL clock generation applications. These devices use an external
high Q fundamental mode pullable crystal and Phase Locked Loop
(PLL) multiplier to provide a wide range of frequencies from 60 MHz
to 700 MHz (factory configurable per user specifications) with a
pullable range of
±100
ppm. The silicon−based PureEdge products
provides users with exceptional frequency stability and reliability.
They produce an ultra low jitter and phase noise LVPECL differential
output. The NB3NXXXXX
−
series are members of
ON Semiconductor’s PureEdge clock family that provides accurate
and precision clock generation solutions.
Available in the industry standard 4 mm x 4 mm QFN−20 package.
Features
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MARKING
DIAGRAM
20
1
QFN20
MN SUFFIX
CASE 485E
XXXXX
A
L, WL
Y
W, WW
G or
G
NB3N
xxxxx
ALYWG
G
•
•
•
•
•
•
•
•
•
•
•
•
•
•
LVPECL Differential Output
Operating Range: 3.3 V
±10%
Ultra Low Jitter and Phase Noise
−
0.5 ps (12 kHz
−
20 MHz)
245 ps Typical Rise and Fall Times
Factory Configurable Frequencies from 60 MHz to 700 MHz (see
Standard Frequencies in the Ordering Information Table in page 5)
Pullable Range Minimum of
±100
ppm
Control Voltage with Positive Slope
−40°C
to +85°C Ambient Operating Temperature
These Devices are Pb−Free and are RoHS Compliant
Networking
SONET
10 Gigabit Ethernet
Networking Base Stations
Broadcasting
= Frequency XXX.XX
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(*Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 5 of this data sheet.
XIN
V
C
OE
XOUT
V
DD
PLL
Clock
Multiplier
CLK
Applications
GND
CLK
Figure 1. Simplified Block Diagram of
NB3Nxxxxx
©
Semiconductor Components Industries, LLC, 2012
April, 2012
−
Rev. 0
1
Publication Order Number:
NB3N15552MN/D
NB3Nxxxxx
−
VCXO Series
Exposed Pad
nc
20
XIN
19
nc XOUT
18
17
nc
16
Table 1. OUTPUT ENABLE TRI−STATE FUNCTION
OE
Open
High
Output Pins Function
Active
Active
High Z
V
C
OE
GND
GND
GND
1
2
3
4
5
15
14
13
12
11
V
DD
V
DD
V
DD
CLK
CLK
Low
6
nc
7
nc
8
nc
9
nc
10
nc
Figure 2. QFN−20 Pinout
(Top View)
Table 2. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Name
VC
OE
GND
GND
GND
nc
nc
nc
nc
nc
CLK
CLK
VDD
VDD
VDD
nc
XOUT
nc
XIN
I/O
Analog Input
LVTTL /
LVCMOS Input
Ground
Ground
Ground
No connect
No connect
No connect
No connect
No connect
LVPECL Output
LVPECL Output
Power Supply
Power Supply
Power Supply
No connect
Crystal
No connect
Crystal
Crystal Input. This pin forms an oscillator when connected to an external parallel−resonant
crystal.
Crystal Input. This pin forms an oscillator when connected to an external parallel−resonant
crystal.
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to V
DD
– 2 V.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
DD
– 2 V.
3.3 V Positive Supply Voltage
3.3 V Positive Supply Voltage
3.3 V Positive Supply Voltage
Description
Analog control voltage input pin that adjusts output oscillation frequency. f0 = V
C
= 1.65 V.
Control voltage has a positive slope with a linearity of
±10%;
V
C
= 1.65 V
±
1 V.
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 1.
Negative Supply Voltage
Negative Supply Voltage
Negative Supply Voltage
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2
NB3Nxxxxx
−
VCXO Series
Table 2. PIN DESCRIPTION
Pin
20
−
Name
nc
EP
I/O
No connect
The Exposed Pad (EP) on the QFN−20 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is electrically connected to the die, and must be electrically and thermally
connected to GND on the PC board.
Description
1. All VDD and GND pins must be externally connected to a power supply for proper operation.
Table 3. ATTRIBUTES
Characteristics
Internal Default State Resistor (OE)
ESD Protection Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Value
170 kW
2 kV
200 V
Level 1
UL 94 V−0 @ 0.125 in
3510 Devices
Table 4. MAXIMUM RATINGS
Symbol
V
DD
V
IN
I
OUT
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Control Input (V
C
and OE)
LVPECL Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
(Note 3)
Wave Solder Pb−Free
0 lfpm
500 lfpm
Standard Board
QFN−20
QFN−20
QFN−20
Continuous
Surge
Condition 1
GND = 0 V
V
IN
≤
V
DD
+ 200 mV
V
IN
≥
GND
−
200 mV
25
50
−40
to +85
−55
to +120
47
33
18
265
Condition 1
Rating
4.6
Unit
V
V
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
Table 5. RECOMMENDED CRYSTAL PARAMETERS
Crystal Type
Frequency
Load Capacitance
Shunt Capacitance, C0
Motional Capacitance (C1)
Capacitance Ratio (C0/C1)
ESR (Equivalent Series Resistance)
Fundamental AT−Cut
Various
−
Device dependent; see AC Table
16 pF
3.2 pF typical
12 fF typical
260 typical
25
W
max; 5
W
typical
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3
NB3Nxxxxx
−
VCXO Series
Table 6. DC CHARACTERISTICS
(VDD = 3.3 V
±
10%, GND = 0 V, TA =
−40
°
C to +85
°
C) (Note 4)
Symbol
IDD
VIH
VIL
IIH
IIL
VOH
VOL
VOUTPP
Power Supply Current
Input HIGH Voltage, OE
Input LOW Voltage, OE
Input HIGH Current, OE
Input LOW Current, OE
Output HIGH Voltage
Output LOW Voltage
Output Voltage Amplitude
2000
GND
−
200
−100
−100
V
DD
−
1195
V
DD
−
1945
700
Characteristic
Min
Typ
90
Max
110
V
DD
800
+100
+100
V
DD
−
945
V
DD
−
1600
Unit
mA
mV
mV
uA
uA
mV
mV
mV
4. Measurement taken with outputs terminated with 50
W
to V
DD
−
2.0 V. See Figure 3.
Table 7. AC CHARACTERISTICS
(V
DD
= 3.3
±10%,
GND = 0 V, T
A
=
−40°C
to +85°C)
Symbol
f
CLKOUT
Characteristic
Output Clock Frequency
Crystal fref = 28.276363 MHz
Crystal fref = 28.409090 MHz
Crystal fref = 30.703125 MHz
Crystal fref = 28.276363 MHz
t
jit(cp)
t
jitter
RMS Phase Jitter
Cycle to Cycle, RMS
Cycle to Cycle, Peak−to−Peak
Period, RMS
Period, Peak−to−Peak
t
OE/OD
F
P
V
C(bw)
Output Enable/Disable Time
Crystal Pull ability (Note 5)
Control Voltage Bandwidth
0
≤
V
C
≤
3.3 V
−3
dB
±100
20
45
50
245
245
1
55
400
400
5
Conditions
NB3N15552
NB3N15625
NB3N49152
NB3N62208
12 kHz to 20 MHz
1000 Cycles
1000 Cycles
10,000 Cycles
10,000 Cycles
Min
Typ
155.52
156.25
491.52
622.08
0.5
2
10
1
6
0.9
8
30
4
20
200
ns
ppm
kHz
%
ps
ps
ms
ps
ps
Max
Unit
MHz
t
DUTY_CYCLE
Output Clock Duty Cycle
(Measured at Cross Point)
t
R
t
F
t
start
Output Rise Time (20% and 80%)
Output Fall Time (80% and 20%)
Start−up Time
5. Gain transfer is positive with a rate of 130 ppm/V.
Table 8. PHASE NOISE PERFORMANCE
Parameter
q
NOISE
Characteristic
Output Phase-Noise Performance
Condition
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
155.52 MHZ 156.25 MHz 491.52 MHz 622.08 MHZ
−82
−106
−126
−128
−135
−159
−82
−106
−126
−128
−135
−159
−72
−96
−116
−119
−125
−151
−70
−94
−114
−116
−123
−149
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
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NB3Nxxxxx
−
VCXO Series
ORDERING INFORMATION
Device
NB3N15552MNG
NB3N15552MNTXG
NB3N15625MNG
NB3N15625MNTXG
NB3N49152MNG
NB3N49152MNTXG
NB3N62208MNG
NB3N62208MNTXG
Frequency (MHz)
155.52
155.52
156.25
156.25
491.52
491.52
622.08
622.08
Package
QFN−20
(Pb−Free)
QFN−20
(Pb−Free)
QFN−20
(Pb−Free)
QFN−20
(Pb−Free)
QFN−20
(Pb−Free)
QFN−20
(Pb−Free)
QFN−20
(Pb−Free)
QFN−20
(Pb−Free)
Shipping
†
92 Units / Rail
3000 / Tape & Reel
92 Units / Rail
3000 / Tape & Reel
92 Units / Rail
3000 / Tape & Reel
92 Units / Rail
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NB3NXXXXX
Q
Driver
Device
Q
Z
o
= 50
W
50
W
50
W
D
Z
o
= 50
W
D
Receiver
Device
V
TT
V
TT
= V
DD
−
2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
−
Termination of ECL Logic Devices.)
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