Z87200
Spread-Spectrum
Transceiver
Product Specification
PS010202-0601
ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008
Telephone: 408.558.8500 • Fax: 408.558.8300 •
www.ZiLOG.com
Z87200
Spread-Spectrum Transceiver
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PS010202-0601
P
RODUCT
S
PECIFICATION
4
Z87200
S
PREAD
-S
PECTRUM
T
RANSCEIVER
FEATURES
Min
PN Rate*
Max Data
Speed
(Mchips) Rate* (Mbps) (MHz) Package
11
2.048
20/45
100-Pin
PQFP
s
4
Full- or Half-Duplex Operation
Device
Z87200
Benefits
s
High Performance and High Reliability for Reduced
Manufacturing Costs
Ideal for a Wide Range of Wireless Applications
Including Data Acquisition Systems, Transaction
Systems, and Wireless Local Area Networks (WLANs)
Fast Response and Very Low Overhead when
Operating in Burst Modes
Allows High Processing Gain to Maximize the
Acquisition Probability, then Reduced Code Length for
Increased Data Rate
Reduced Power Consumption
Randomizes Data to Meet Regulatory Requirements
Permits Dual Frequency (Frequency Division Duplex) or
Single Frequency (Time Division Duplex) Operation
Small Footprint, Surface Mount
Note:
*45 MHz only
s
s
Complete
Direct
Sequence
Transceiver in a Single CMOS IC
Spread-Spectrum
s
s
Programmable Functionality Supports Many Different
Operational Modes
Acquires Within One Symbol Duration Using Digital PN
Matched Filter
Two Independent PN Sequences, Each up to 64 Chips
Long for Distinct Processing of the Acquisition/Preamble
Symbol and Subsequent Data Symbols
Power Management Features
Optional Spectral Whitening Code Generation
s
s
s
s
s
s
s
s
s
GENERAL DESCRIPTION
The Z87200 is a programmable single-chip, spread-spec-
trum, direct-sequence transceiver. The Z87200 incorpo-
rates Stanford Telecom spread-spectrum and wireless
technology and is identical to Stanford Telecom's STEL-
2000A. By virtue of its fast acquisition capabilities and its
ability to support a wide range of data rates and spread-
spectrum parameters, the Z87200 spread-spectrum trans-
ceiver supports the implementation of a wide range of
burst data communications applications.
Available in both 45- and 20-MHz versions, the Z87200
performs all the digital processing required to implement a
fast-acquisition direct sequence (such as pseudonoise- or
PN-modulated), spread-spectrum full- or half-duplex sys-
tem. Differentially encoded BPSK and QPSK are fully sup-
ported. The receiver section can also handle differentially
encoded pi/4 QPSK. A block diagram of the Z87200 is
shown in Figure 1; its pin configuration is shown in Z87200
receive functions integrate the capabilities of a digital
downconverter, PN matched filter, and DPSK demodula-
tor, where the input signal is an analog-to-digital converted
I.F. signal. Z87200 transmit functions include a differential
BPSK/QPSK encoder, PN modulator (spreader), and
BPSK/QPSK modulator, where the transmitter output is a
sampled digitally modulated signal ready for external digi-
PS010202-0601
4-1
Z87200
Spread-Spectrum Transceiver
Zilog
GENERAL DESCRIPTION
(Continued)
tal-to-analog conversion (or, if preferred, the spread base-
band signal may be output to an external modulator).
These transceiver functions have been designed and inte-
grated for the transmission and reception of bursts of
spread data. In particular, the PN Matched Filter has two
distinct PN coefficient registers (rather than a single one)
in order to speed and improve signal acquisition perfor-
mance by automatically switching from one to the other
upon signal acquisition. The Z87200 is thus optimized to
provide reliable, high-speed wireless data communica-
tions.
The data rate R
b
and the PN code length N, however, can-
not generally be arbitrarily chosen. United States FCC Part
15.247 regulations require a minimum processing gain of
10 dB for unlicensed operation in the Industrial, Scientific,
and Medical (ISM) bands, implying that the value of N must
be at least 10. To implement such a short code, a Barker
code of length 11 would typically be used in order to obtain
desirable auto- and cross-correlation properties, although
compliance with FCC regulations depends upon the over-
all system implementation. The Z87200 further includes
transmit and receive code overlay generators to insure
that signals spread with such a short PN code length pos-
sess the spectral properties required by FCC regulations.
The receiver clock rate established by RXIFCLK must be
at least four times the receive PN spreading rate and is lim-
ited to a maximum speed of 45.056 MHz in the 45 MHz
Z87200 and 20.0 MHz in the 20 MHz Z87200. The ensuing
discussion is in terms of the 45 MHz Z87200, but the nu-
merical values may be scaled proportionately for the 20
MHz version. As a result of the maximum 45.056 MHz RX-
IFCLK, the maximum supported PN chip rate is 11.264
Mchips/second. When operating with BPSK modulation,
the maximum data rate for a PN code of length N is
11.264/N Mbps. When operating with QPSK modulation
(or
π
/4 QPSK with an external modulator), two bits of data
are transmitted per symbol, and the data rate for a PN
code of length N is 22.528/N Mbps. Conversely, for a given
data rate R
b
, the length N of the PN code employed must
be such that the product of N x R
b
is less than 11.264
Mchips/sec (for BPSK) or 22.528 Mchips/sec (for QPSK).
For the 45 MHz Z87200, then, a PN code length of 11 im-
plies that the maximum data rate that can be supported in
compliance with the processing gain requirements of FCC
regulations is 2.048 Mbps using differential QPSK. Note
again, however, that FCC compliance using the Z87200
with a PN code of length 11 depends upon the overall sys-
tem implementation.
Symbol-Synchronous PN Modulation
The Z87200 operates with symbol-synchronous PN mod-
ulation in both transmit and receive modes. Symbol-syn-
chronous PN modulation refers to operation where the PN
code is aligned with the symbol transitions and repeats
once per symbol. By synchronizing a full PN code cycle
over a symbol duration, acquisition of the PN code at the
receiver simultaneously provides symbol synchronization,
thereby significantly improving overall acquisition time.
As a result of the Z87200's symbol-synchronous PN mod-
ulation, the data rate is defined by the PN chip rate and
length of the PN code; that is, by the number of chips per
symbol, where a “chip” is a single “bit” of the PN code. The
PN chip rate, R
c
chips/second, is programmable to as
much as 1/4 the rate of RXIFCLK, and the PN code length,
N, can be programmed up to a value of 64. When operat-
ing with BPSK modulation, the data rate for a PN code of
length N and PN chip rate R
C
chips/sec is R
C
/N bps. When
operating with QPSK modulation (or
π
/4 QPSK with an ex-
ternal modulator), two bits of data are transmitted per sym-
bol, and the data rate for a PN code of length N and PN
chip rate R
c
chips/sec is 2R
c
/N bps. Conversely, for a giv-
en data rate R
b
bps, the length N of the PN code defines
the PN chip rate R
c
as N x R
b
chips/sec for BPSK or as (N
x R
b
)/2 chips/sec for QPSK.
4-2
PS010202-0601
Zilog
Z87200
Spread-Spectrum Transceiver
To improve performance in the presence of high noise and
interference levels, the Z87200 receiver’s symbol timing
recovery circuit incorporates a “flywheel circuit” to maxi-
mize the probability of correct symbol timing. This circuit
will insert a symbol clock pulse if the correlation peak ob-
tained by the PN Matched Filter fails to exceed the pro-
grammed detect threshold at the expected time during a
given symbol. During each burst, a missed detect counter
tallies each such event to monitor performance and allow
a burst to be aborted in the presence of abnormally high in-
terference. A timing gate circuit further minimizes the prob-
ability of false correlation peak detection and consequent
false symbol clock generation due to noise or interference.
To minimize power consumption, individual sections of the
device can be turned off when not in use. For example, the
receiver circuitry can be turned off during transmission
and, conversely, the transmitter circuitry can be turned off
during reception when the Z87200 is operating in a half-
duplex/time division duplex (TDD) system. If the NCO is
not being used as the BPSK/QPSK modulator (that is, if an
external modulator is being used), the NCO can also be
turned off during transmission to conserve still more pow-
er.
Z87200 I.F. Interface
The Z87200 receiver circuitry employs an NCO and com-
plex multiplier referenced to RXIFCLK to perform frequen-
cy downconversion, where the input I.F. sampling rate and
the clock rate of RXIFCLK must be identical. In “complex
input” or Quadrature Sampling Mode, external dual ana-
log-to-digital converters (ADCs) sample quadrature I.F.
signals so that the Z87200 can perform true full single
sideband downconversion directly from I.F. to baseband.
At PN chip rates less than one-eighth the value of RXIF-
CLK, downconversion may also be effected using a single
ADC in “real input” or Direct I.F. Sampling Mode.
The input I.F. frequency is not limited by the capabilities of
the Z87200. The highest frequency to which the NCO can
be programmed is 50% of the I.F. sampling rate (the fre-
quency of RXIFCLK); moreover, the signal bandwidth,
NCO frequency, and I.F. sampling rate are all interrelated,
as discussed in Higher I.F. frequencies, however, can be
supported by using one of the aliases of the NCO frequen-
cy generated by the sampling process. For example, a
spread signal presented to the Z87200’s receiver ADCs at
an I.F. frequency of f
I.F.
, where f
RXIFCLK
< f
I.F.
< 2 x f
RXIF-
CLK
, can generally, as allowed by the signal’s bandwidth,
be supported by programming the Z87200’s NCO to a fre-
quency of (f
I.F.
- f
RXIFCLK
), as discussed in Appendix A of
this product specification. The maximum I.F. frequency is
then limited by the track-and-hold capabilities of the
ADC(s) selected. Signals at I.F. frequencies up to about
100 MHz can be processed by currently available 8-bit
ADCs, but the implementation cost as well as the perfor-
mance can typically be improved by using an I.F. frequen-
cy of 30 MHz or lower. Downconversion to baseband is
then accomplished digitally by the Z87200, with a pro-
grammable loop filter provided to establish a frequency
tracking loop.
4
Conclusion
The fast acquisition characteristics of the Z87200 make it
ideal for use in applications where bursts are transmitted
relatively infrequently. In such cases, the device can be
controlled so that it is in full “sleep” mode with all receiver,
transmitter, and NCO functions turned off over the majority
of the burst cycle, thereby significantly reducing the aggre-
gate power consumption. Since the multiply operations of
the PN Matched Filter consume a major part of the overall
power required during receiver operation, two independent
power-saving techniques are also built into the PN
Matched Filter to reduce consumption during operation by
a significant factor for both short and long PN spreading
codes.
The above features make the Z87200 an extremely
versatile and useful device for spread-spectrum data
communications. Operating at its highest rates, the
Z87200 is suitable for use in wireless Local Area Network
implementations, while its programmability allows it to be
used in a variety of data acquisition, telemetry, and
transaction system applications.
Burst and Continuous Data Modes
The Z87200 is designed to operate in either burst or con-
tinuous mode: in burst mode, built-in symbol counters al-
low bursts of up to 65,533 symbols to be automatically
transmitted or received; in continuous mode, the data is
simply treated as a burst of infinite length. The Z87200’s
use of a digital PN Matched Filter for code detection and
despreading permits signal and symbol timing acquisition
in just one symbol. The fast acquisition properties of this
design are exploited by preceding each data burst with a
single Acquisition/Preamble symbol, allowing different PN
codes (at the same PN chip rate) to independently spread
the Acquisition/Preamble and data symbols. In this way, a
long PN code with high processing gain can be used for
the Acquisition/Preamble symbol to maximize the proba-
bility of burst detection, and a shorter PN code can be used
thereafter to permit a higher data rate.
PS010202-0601
4-3
Analog electronics
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