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EPM7160ELC84-15

Description
CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 160 Macro 64 IOs
CategoryProgrammable logic devices    Programmable logic   
File Size462KB,66 Pages
ManufacturerAltera (Intel)
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EPM7160ELC84-15 Overview

CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 160 Macro 64 IOs

EPM7160ELC84-15 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeLCC
package instructionPLASTIC, LCC-84
Contacts84
Reach Compliance Codeunknown
ECCN codeEAR99
Is SamacsysN
Other featuresCONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
maximum clock frequency100 MHz
In-system programmableNO
JESD-30 codeS-PQCC-J84
JESD-609 codee0
JTAG BSTNO
length29.3116 mm
Humidity sensitivity level2
Dedicated input times
Number of I/O lines64
Number of macro cells160
Number of terminals84
Maximum operating temperature70 °C
Minimum operating temperature
organize0 DEDICATED INPUTS, 64 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC84,1.2SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)220
power supply3.3/5,5 V
Programmable logic typeEE PLD
propagation delay15 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width29.3116 mm
Base Number Matches1
MAX 7000
®
Programmable Logic
Device Family
Data Sheet
September 2005, ver. 6.7
Features...
High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX
®
architecture
5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see
Tables 1
and
2)
5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
f
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the
MAX 7000A Programmable Logic Device Family
Data Sheet
or the
MAX 7000B Programmable Logic Device Family Data
Sheet.
Table 1. MAX 7000 Device Features
Feature
Usable
gates
Macrocells
Logic array
blocks
Maximum
user I/O pins
t
PD
(ns)
t
SU
(ns)
t
FSU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
EPM7032
600
32
2
36
6
5
2.5
4
151.5
EPM7064
1,250
64
4
68
6
5
2.5
4
151.5
EPM7096
1,800
96
6
76
7.5
6
3
4.5
125.0
EPM7128E
2,500
128
8
100
7.5
6
3
4.5
125.0
EPM7160E
3,200
160
10
104
10
7
3
5
100.0
EPM7192E
3,750
192
12
124
12
7
3
6
90.9
EPM7256E
5,000
256
16
164
12
7
3
6
90.9
Altera Corporation
DS-MAX7000-6.7
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