4-Bit, 2:1, Single-Ended Multiplexer
83054I-01
Datasheet
G
ENERAL
D
ESCRIPTION
The 83054I-01 is a 4-bit, 2:1, Single-ended Multiplexer and a
member of the family of High Performance Clock Solutions from
IDT. The 83054I-01 has two selectable single-ended clock inputs
and four single-ended clock outputs. The output has a V
DDO
pin
which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal
for use in voltage translation applications. An output enable pin
places the output in a high impedance state which may be useful
for testing or debug. Possible applications include systems with up
to four transceivers which need to be independently set for different
rates. For example, a board may have four transceivers, each of
which need to be independently configured for 1 Gigabit Ethernet
or 1 Gigabit Fibre Channel rates. Another possible application may
require the ports to be independently set for FEC (Forward Error
Correction) or non-FEC rates. The device operates up to 250MHz
and is packaged in a 16 TSSOP.
F
EATURES
• Four-bit, 2:1 single-ended multiplexer
• Nominal output impedance: 15Ω (V
DDO
= 3.3V)
• Maximum output frequency: 250MHz
• Propagation delay: 3.2ns (maximum), V
DD
= V
DDO
= 3.3V
• Input skew: 170ps (maximum), V
DD
= V
DDO
= 3.3V
• Output skew: 90ps (maximum), V
DD
= V
DDO
= 3.3V
• Part-to-part skew: 800ps (maximum), V
DD
= V
DDO
= 3.3V
• Additive phase jitter, RMS at 155.52MHz, (12kHz – 20MHz):
0.18ps (typical)
• Operating supply modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
SEL0 Pulldown
P
IN
A
SSIGNMENT
SEL3
Q3
V
DDO
GND
Q2
SEL2
CLK1
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0
Q0
V
DDO
GND
Q1
SEL1
CLK0
OE
CLK0
Pulldown
0
Q0
CLK1
Pulldown
1
0
Q3
83054I-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
1
SEL3 Pulldown
OE Pullup
©2015 Integrated Device Technology, Inc
1
December 15, 2015
83054I-01 Datasheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 6
11, 16
2, 5, 12, 15
3, 14
4, 13
7, 10
8
9
Name
SEL3, SEL2,
SEL1, SEL0
Q3, Q2, Q1, Q0
V
DDO
GND
CLK1, CLK0
V
DD
OE
Input
Output
Power
Power
Input
Power
Input
Pullup
Type
Pulldown
Description
Clock select inputs. See Control Input Function Table.
LVCMOS / LVTTL interface levels.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output supply pins.
Power supply ground.
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Positive supply pin.
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 2.0V
V
DDO
= 3.465V
R
OUT
Output Impedance
V
DDO
= 2.625V
V
DDO
= 2.0V
Test Conditions
Minimum
Typical
4
51
51
18
19
19
15
17
25
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Control Inputs
SELx
0
1
Outputs
Qx
CLK0
CLK1
©2015 Integrated Device Technology, Inc
2
December 15, 2015
83054I-01 Datasheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
100.3°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%,
OR
2.5V±5%,
OR
1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
3.135
2.375
1.6
Typical
3.3
3.3
2.5
1.8
Maximum
3.465
3.465
2.625
2.0
45
5
Units
V
V
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 2.5V±5%,
OR
1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
2.375
2.375
1.6
Typical
2.5
2.5
1.8
Maximum
2.625
2.625
2.0
40
5
Units
V
V
V
mA
mA
©2015 Integrated Device Technology, Inc
3
December 15, 2015
83054I-01 Datasheet
T
ABLE
4C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK0, CLK1,
SEL0:SEL3
OE
I
IL
Input Low Current
CLK0, CLK1,
SEL0:SEL3
OE
V
OH
Output HighVoltage; NOTE 1
Test Conditions
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DDO
= 3.3V ± 5%
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
V
DDO
= 3.3V ± 5%
V
OL
Output Low Voltage; NOTE 1
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
-5
-150
2.6
1.8
V
DD
- 0.3
0.5
0.45
0.35
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
Input High Current
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement section, “Load Test Circuit” diagrams.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tp
LH
tp
HL
tsk(o)
tsk(i)
tsk(pp)
tjit
t
R
/ t
F
odc
MUX
ISOL
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Output Skew; NOTE 2, 3
Input Skew; NOTE 2
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
155.52, Integration Range:
12kHz – 20MHz
20% to 80%
ƒout
≤
175MHz
@100MHz
300
40
45
0.18
800
60
1.8
2.0
2.5
2.6
30
40
Test Conditions
Minimum
Typical
Maximum
250
3.2
3.2
90
170
800
Units
MHz
ns
ns
ps
ps
ps
ps
ps
%
dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltags and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: Driving only one input clock.
©2015 Integrated Device Technology, Inc
4
December 15, 2015
83054I-01 Datasheet
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tp
LH
tp
HL
tsk(o)
tsk(i)
tsk(pp)
tjit
t
R
/ t
F
odc
MUX
ISOL
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Output Skew; NOTE 2, 3
Input Skew; NOTE 2
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
@100MHz
155.52, Integration Range:
12kHz – 20MHz
20% to 80%
300
40
45
0.14
800
60
2.1
2.3
2.6
2.7
40
35
Test Conditions
Minimum
Typical
Maximum
250
3.1
3.1
125
190
800
Units
MHz
ns
ns
ps
ps
ps
ps
ps
%
dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltags and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: Driving only one input clock.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tp
LH
tp
HL
tsk(o)
tsk(i)
tsk(pp)
tjit
t
R
/ t
F
odc
MUX
ISOL
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Output Skew; NOTE 2, 3
Input Skew; NOTE 2
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
@100MHz
155.52, Integration Range:
12kHz – 20MHz
20% to 80%
450
40
45
0.16
850
60
2.6
2.7
3.1
3.2
40
35
Test Conditions
Minimum
Typical
Maximum
250
3.6
3.7
125
195
800
Units
MHz
ns
ns
ps
ps
ps
ps
ps
%
dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltags and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: Driving only one input clock.
©2015 Integrated Device Technology, Inc
5
December 15, 2015
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