14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
3 V A/D Converte
r
Data Sheet
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 72.7 dBc to Nyquist
SFDR = 83.0 dBc to Nyquist
Low power
366 mW at 80 MSPS
300 mW at 65 MSPS
165 mW at 40 MSPS
90 mW at 20 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ±0.5 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty-cycle stabilizer
AVDD
AD9245
FUNCTIONAL BLOCK DIAGRAM
DRVDD
AD9245
VIN+
SHA
VIN–
4
REFT
REFB
CORRECTION LOGIC
14
OUTPUT BUFFERS
D13 (MSB)
VREF
D0 (LSB)
SENSE
REF
SELECT
0.5V
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
03583-001
MDAC1
8-STAGE
1 1/2-BIT PIPELINE
16
A/D
3
A/D
OTR
APPLICATIONS
Medical imaging equipment
IF sampling in communications receivers
WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA
Battery-powered instruments
Hand-held scopemeters
Spectrum analyzers
Power-sensitive military applications
AGND
CLK
PDWN
MODE DGND
Figure 1.
GENERAL DESCRIPTION
The AD9245 is a monolithic, single 3 V supply, 14-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital
converter (ADC) featuring a high performance sample-and-
hold amplifier (SHA) and voltage reference. The AD9245 uses a
multistage differential pipelined architecture with output error
correction logic to provide 14-bit accuracy and guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9245 is
suitable for applications in communications, imaging, and
medical ultrasound.
A single-ended clock input is used to control all internal con-
version cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9245 is available in a 32-lead LFCSP and is specified over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9245 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
2. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
3. The AD9245 is pin-compatible with the AD9215, AD9235,
and AD9236. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
4. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
5. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev. E
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Trademarks and registered trademarks are the property of their respective owners.
AD9245
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 8
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Terminology .................................................................................... 10
Pin Configuration and Function Descriptions ........................... 11
Equivalent Circuits ......................................................................... 12
Data Sheet
Typical Performance Characteristics ........................................... 13
Theory of Operation ...................................................................... 18
Analog Input and Reference Overview ................................... 18
Clock Input Considerations ...................................................... 19
Jitter Considerations .................................................................. 20
Power Dissipation and Standby Mode .................................... 20
Digital Outputs ........................................................................... 20
Timing.......................................................................................... 21
Voltage Reference ....................................................................... 21
Internal Reference Connection ................................................ 21
External Reference Operation .................................................. 22
Operational Mode Selection ..................................................... 22
Evaluation Board ........................................................................ 22
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
5/13—Rev. D to Rev. E
Changed CP-32-2 to CP-32-7 ........................................... Universal
Changes to Figure 3 and Table 9 ................................................... 11
Changes to Figure 40 ...................................................................... 19
Changes to Ordering Guide .......................................................... 29
1/06—Rev. C to Rev. D
Changes to Differential Input Configurations Section and
Figure 40 .......................................................................................... 19
Changes to Internal Reference Connection Section .................. 21
Changes to Figure 49 ...................................................................... 23
Changes to Figure 50 ...................................................................... 24
Changes to Table 12 ........................................................................ 28
Updated Outline Dimensions ....................................................... 29
Changes to Ordering Guide .......................................................... 29
8/05—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Features, Applications, General Description, and
Product Highlights ........................................................................... 1
Added Table 1; Renumbered Sequentially .................................... 3
Changes to Table 2 ............................................................................ 4
Added Table 3; Renumbered Sequentially .................................... 5
Changes to Table 4 ............................................................................ 6
Changes to Table 5.............................................................................7
Changes to Table 6.............................................................................8
Deleted Explanation of Test Levels Table .......................................8
Added Figure 26 to Figure 31; Renumbered Sequentially ........ 16
Added Figure 32 to Figure 37; Renumbered Sequentially ........ 17
Changes to Figure 39...................................................................... 18
Changes to Clock Input Consideration Section ......................... 19
Changes to Figure 44...................................................................... 20
Changes to Table 10 ....................................................................... 21
Changes to Figure 51...................................................................... 25
Changes to Table 12 ....................................................................... 28
Changes to Ordering Guide .......................................................... 29
Updated Outline Dimensions ....................................................... 29
10/03—Rev. A to Rev. B
Changes to Figure 33...................................................................... 17
5/03—Rev. 0 to Rev. A
Changes to Figure 30...................................................................... 15
Changes to Figure 37...................................................................... 19
Changes to Figure 38...................................................................... 20
Changes to Figure 39...................................................................... 21
Changes to Table 10 ....................................................................... 24
Changes to the Ordering Guide ................................................... 25
Rev. E | Page 2 of 32
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AD9245
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
TEMPERATURE DRIFT
1
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance
3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD
2
IDRVDD
2
PSRR
POWER CONSUMPTION
DC Input
4
Sine Wave Input
2
Standby Power
5
1
2
AD9245BCP-20
Min
Typ
Max
14
14
±0.30
±0.30
±0.50
±1.20
±2
±12
±5
0.8
±2.5
0.1
2.28
1.08
1
2
7
7
±35
±1.60
±3.25
±1.00
±3.10
AD9245BCP-40
Min
Typ
Max
14
14
±0.50
±0.50
±0.50
±1.40
±2
±12
±5
0.8
±2.5
0.1
2.28
1.08
1
2
7
7
±35
±1.75
±3.25
±1.00
±3.40
AD9245BCP-65
Min
Typ
Max
14
14
±0.50
±0.50
±0.50
±1.60
±3
±12
±5
0.8
±2.5
0.1
2.28
1.08
1
2
7
7
±35
±1.75
±6.90
±1.00
±5.55
Unit
Bits
Bits
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
mV
mV
mV
mV
LSB rms
LSB rms
V p-p
V p-p
pF
kΩ
2.7
2.25
3.0
3.0
30
2
±0.01
90
95
1.0
3.6
3.6
2.7
2.25
3.0
3.0
55
5
±0.01
165
180
1.0
3.6
3.6
2.7
2.25
3.0
3.0
100
7
±0.01
300
320
1.0
3.6
3.6
V
V
mA
mA
% FSR
mW
mW
mW
120
220
375
Gain errors and gain temperature coefficients are based on the ADC only (with a fixed 1.0 V external reference).
Measured at maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with a dc input, the CLK pin inactive (that is, set to AVDD or AGND).
Rev. E | Page 3 of 32
AD9245
Table 2.
AD9245BCP-80
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
1
Gain Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
TEMPERATURE DRIFT
Offset Error
1
Gain Error
Gain Error
1
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance
3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD
2
IDRVDD
2
PSRR
POWER CONSUMPTION
Low Frequency Input
4
Standby Power
5
1
2
Data Sheet
AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted.
Min
14
Typ
Max
Unit
Bits
Guaranteed
±0.30
±0.28
±0.70
±0.5
±1.4
±10
±12
±17
±3
±2
±6
±1
1.86
1.17
1
2
7
7
±1.2
±4.16
±1.0
±5.15
% FSR
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
±34
mV
mV
mV
mV
LSB rms
LSB rms
V p-p
V p-p
pF
kΩ
2.7
2.25
3.0
2.5
122
9
±0.01
366
1.0
3.6
3.6
138
V
V
mA
mA
% FSR
mW
mW
With a 1.0 V internal reference.
Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 4 for the equivalent analog input structure.
4
Measured at ac specification conditions without output drivers.
5
Standby power is measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND).
Rev. E | Page 4 of 32
Data Sheet
AC SPECIFICATIONS
AD9245
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, DCS off,
unless otherwise noted.
Table 3.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
f
INPUT
= 2.4 MHz
f
INPUT
= 9.7 MHz
f
INPUT
= 19.6 MHz
f
INPUT
= 32.5 MHz
f
INPUT
= 100 MHz
SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD)
f
INPUT
= 2.4 MHz
f
INPUT
= 9.7 MHz
f
INPUT
= 19.6 MHz
f
INPUT
= 32.5 MHz
f
INPUT
= 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
INPUT
= 9.7 MHz
f
INPUT
= 19.6 MHz
f
INPUT
= 32.5 MHz
WORST HARMONIC (SECOND OR THIRD)
f
INPUT
= 9.7 MHz
f
INPUT
= 19.6 MHz
f
INPUT
= 32.5 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
INPUT
= 2.4 MHz
f
INPUT
= 9.7 MHz
f
INPUT
= 19.6 MHz
f
INPUT
= 32.5 MHz
f
INPUT
= 100 MHz
AD9245BCP-20
Min
Typ
Max
73.5
73.3
70.5
70.8
73.4
73.2
70.0
69.5
11.9
11.8
11.7
–89
–80
–89
–80
–83
92.0
89.0
80.0
84.0
92.0
89.0
74.0
85.0
83.0
80.5
92.0
–74
AD9245BCP-40
Min
Typ
Max
73.5
73.4
70.3
71.3
73.4
73.2
68.4
69.1
72.6
67.9
72.7
70.2
73.0
AD9245BCP-65
Min
Typ
Max
73.1
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
70.6
69.4
80.0
Rev. E | Page 5 of 32
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