S29AL016D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
Data Sheet
PRELIMINARY
Distinctive Characteristics
Architectural Advantages
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write op-
erations for battery-powered applications
Ultra low power consumption (typical values
at 5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 20 mA program/erase current
Manufactured on 200nm process technology
— Fully compatible with 0.23 µm Am29LV160D and
MBM29LV160E devices
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-
one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and thirty-
one 32 Kword sectors (word mode)
Cycling endurance: 1,000,000 cycles per
sector typical
Data retention: 20 years typical
Package Options
48-ball FBGA
48-pin TSOP
44-pin SOP
Sector Protection features
— A hardware method of locking a sector to prevent any
program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Software Features
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Top or bottom boot block configurations
available
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
Hardware Features
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Performance Characteristics
High performance
— Access times as fast as 70 ns
Publication Number
S29AL016D_00
Revision
A
Amendment
2
Issue Date
December 17, 2004
P r e l i m i n a r y
General Description
The S29AL016D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152
bytes or 1,048,576 words. The device is offered in 48-ball FBGA, and 48-pin TSOP
packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8)
data appears on DQ7–DQ0. This device is designed to be programmed in-system
with the standard system 3.0 volt V
CC
supply. A 12.0 V V
PP
or 5.0 V
CC
are not
required for write or erase operations. The device can also be programmed in
standard EPROM programmers.
The device offers access times of 70 ns and 90 ns allowing high speed micropro-
cessors to operate without wait states. To eliminate bus contention the device has
separate chip enable (CE#), write enable (WE#) and output enable (OE#)
controls.
The device requires only a
single 3.0 volt power supply
for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations.
The S29AL016D is entirely command set compatible with the
JEDEC single-
power-supply Flash standard.
Commands are written to the command regis-
ter using standard microprocessor write timings. Register contents serve as input
to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This
initiates the
Embedded Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass
mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates
the
Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) before executing the erase
operation. During erase, the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by
observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (tog-
gle)
status bits.
After a program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The
sector erase architecture
allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. The
hardware sector
protection
feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.
The
Erase Suspend/Erase Resume
feature enables the user to put erase on
hold for any period of time to read data from, or program data to, any sector that
is not selected for erasure. True background erase can thus be achieved.
2
S29AL016D
S29AL016D_00_A2 December 17, 2004
P r e l i m i n a r y
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6
Special Handling Instructions ...............................................................7
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
S29AL016D Standard Products ........................................................... 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. S29AL016D Device Bus Operations .........................10
DQ2: Toggle Bit II ................................................................................ 32
Reading Toggle Bits DQ6/DQ2 ........................................................ 32
Figure 6. Toggle Bit Algorithm ............................................ 33
DQ5: Exceeded Timing Limits ...........................................................33
DQ3: Sector Erase Timer .................................................................. 34
Table 10. Write Operation Status ....................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 35
Figure 7. Maximum Negative Overshoot Waveform................ 35
Figure 8. Maximum Positive Overshoot Waveform ................. 35
Word/Byte Configuration ...................................................................10
Requirements for Reading Array Data ............................................ 11
Writing Commands/Command Sequences .................................... 11
Program and Erase Operation Status ............................................... 11
Standby Mode ......................................................................................... 12
Automatic Sleep Mode ......................................................................... 12
RESET#: Hardware Reset Pin ............................................................ 12
Output Disable Mode ........................................................................... 13
Table 2. Sector Address Tables (Top Boot Device) .................13
Table 3. Sector Address Tables (Bottom Boot Device) ............14
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Industrial (I) Devices ............................................................................ 36
V
CC
Supply Voltages ............................................................................ 36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
CMOS Compatible ................................................................................37
Zero Power Flash ................................................................................. 38
Figure 9. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ................................................. 38
Figure 10. Typical I
CC1
vs. Frequency .................................. 38
Figure 11. Test Setup ........................................................ 39
Table 11. Test Specifications ............................................. 39
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Key to Switching Waveforms ...........................................................40
Autoselect Mode ................................................................................... 14
Table 4. S29AL016D Autoselect Codes (High Voltage Method) .15
Figure 12. Input Waveforms and Measurement Levels............ 40
Sector Protection/Unprotection ....................................................... 15
Temporary Sector Unprotect ........................................................... 15
Figure 1. Temporary Sector Unprotect Operation................... 16
Figure 2. In-System Sector Protect/Unprotect Algorithms ....... 17
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
Read Operations .................................................................................... 41
Figure 13. Read Operations Timings .................................... 41
Hardware Reset (RESET#) ................................................................ 42
Figure 14. RESET# Timings ................................................ 42
Common Flash Memory Interface (CFI) . . . . . . . 18
Table 5. CFI Query Identification String ...............................18
Table 6. System Interface String .........................................19
Table 7. Device Geometry Definition ....................................19
Table 8. Primary Vendor-Specific Extended Query .................20
Word/Byte Configuration (BYTE#) ................................................ 43
Figure 15. BYTE# Timings for Read Operations ..................... 43
Figure 16. BYTE# Timings for Write Operations..................... 44
Hardware Data Protection ................................................................20
Low V
CC
Write Inhibit .......................................................................20
Write Pulse “Glitch” Protection ......................................................20
Logical Inhibit .......................................................................................... 21
Power-Up Write Inhibit ...................................................................... 21
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 22
Reading Array Data ............................................................................. 22
Reset Command ................................................................................... 22
Autoselect Command Sequence ...................................................... 23
Word/Byte Program Command Sequence ................................... 23
Unlock Bypass Command Sequence ............................................... 24
Figure 3. Program Operation .............................................. 24
Erase/Program Operations ................................................................ 45
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17. Program Operation Timings ................................. 46
Figure 18. Chip/Sector Erase Operation Timings.................... 47
Figure 19. Data# Polling Timings (During Embedded
Algorithms)...................................................................... 48
Figure 20. Toggle Bit Timings (During Embedded Algorithms) . 48
Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend
Operations ....................................................................... 49
Temporary Sector Unprotect .......................................................... 49
Figure 22. Temporary Sector Unprotect/Timing Diagram ........ 49
Figure 23. Sector Protect/Unprotect Timing Diagram.............. 50
Alternate CE# Controlled Erase/Program Operations ............. 51
Figure 24. Alternate CE# Controlled Write Operation Timings.. 52
Chip Erase Command Sequence ...................................................... 25
Sector Erase Command Sequence .................................................. 25
Erase Suspend/Erase Resume Commands .................................... 26
Figure 4. Erase Operation .................................................. 27
Command Definitions ......................................................................... 28
Table 9. S29AL016D Command Definitions ...........................28
Write Operation Status . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data# Polling .............................................................................. 29
Figure 5. Data# Polling Algorithm ....................................... 30
RY/BY#: Ready/Busy# ......................................................................... 30
DQ6: Toggle Bit I ................................................................................... 31
4
Erase and Programming Performance . . . . . . . . 53
TSOP and BGA Pin Capacitance . . . . . . . . . . . . . 53
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 54
TS 048—48-Pin Standard TSOP ...................................................... 54
VBK048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 mm x 6.15 mm ................................................................................ 56
SO044—44-Pin Small Outline Package (SOP)
28.20 mm x 13.30 mm . . . . . . . . . . . . . . . . . . . . . . . 57
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision A (May 4, 2004) ................................................................... 58
Revision A1 (July 28, 2004) ................................................................. 58
Revision A2 (December 17, 2004) ................................................... 58
S29AL016D_00_A2 December 17, 2004
S29AL016D
FPGA/CPLD
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