S29CD016G0PQAI001 datasheet, PDF

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S29CD016G0PQAI001: Description16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory; File Size990KB，91 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/

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S29CD016G0PQAI001 Overview

16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory

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S29CD016G

16 Megabit (512 K x 32-Bit)

CMOS 2.5 Volt-only Burst Mode, Dual Boot,

Simultaneous Read/Write Flash Memory

Data Sheet

Distinctive Characteristics

Architecture Advantages

Simultaneous Read/Write operations

— Two bank architecture: large bank/ small bank

— Data can be read from bank while executing erase/

program functions in other bank

— Zero latency between read and write operations

User-Defined x32 Data Bus

Dual Boot Block

— Top and bottom boot sectors in the same device

Flexible sector architecture

— Eight 8 Kbytes, thirty 64 Kbytes, and eight 8 Kbytes

sectors

Manufactured on 170 nm process technology

SecSi (Secured Silicon) Sector (256 Bytes)

—

Factory locked and identifiable:

16 bytes for secure,

random factory Electronic Serial Number; remainder

may be customer data programmed by Spansion™

—

Customer lockable:

Can be read, programmed, or

erased just like other sectors. Once locked, data

cannot be changed

Programmable Burst interface

— Interface to any high performance processor

— Modes of Burst Read Operation:

—

Linear Burst:

4 double words and 8 double words

with wrap around

Program Operation

— Ability to perform synchronous and asynchronous

write operations of burst configuration register

settings independently

Single power supply operation

— Optimized for 2.5 to 2.75 volt read, erase, and

program operations

Compatibility with JEDEC standards (JC42.4)

— Software compatible with single-power supply Flash

— Backward-compatible with AMD Am29LV and Am29F

and Fujitsu MBM29LV and MBM29F flash memories

Ultra low power consumption

— Burst Mode Read: 90 mA @ 66 MHz max,

— Program/Erase: 50 mA max

— Standby mode: CMOS: 60 µA max

1 million write cycles per sector typical

20 year data retention typical

VersatileI/O™ control

— Device generates data output voltages and tolerates

data input voltages as determined by the voltage on

the V

— 1.65 V to 2.75 V compatible I/O signals

— 3.6 V tolerant I/O signals

Software Features

Persistent Sector Protection

— A command sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector (requires only V

levels)

Password Sector Protection

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-definable 64-bit password

Supports Common Flash Interface (CFI)

Unlock Bypass Program Command

— Reduces overall programming time when issuing

multiple program command sequences

Data# Polling and toggle bits

— Provides a software method of detecting program or

erase operation completion

Hardware Features

Program Suspend/Resume & Erase Suspend/

Resume

— Suspends program or erase operations to allow

reading, programming, or erasing in same bank

Hardware Reset (RESET#), Ready/Busy# (RY/

BY#), and Write Protect (WP#) inputs

ACC input

— Accelerates programming time for higher throughput

during system production

Package options

— 80-pin PQFP

— 80-ball Fortified BGA

Performance Characteristics

High performance read access

— Initial/random access times as fast as 54 ns

— Burst access time as fast as 9 ns for ball grid array

package

Publication Number

S29CD016_00

Revision

Amendment

Issue Date

November 5, 2004

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion LLC. Spansion

LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided

“as

is” without warranty or guarantee of any

kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or

statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document.

A d v a n c e

I n f o r m a t i o n

Table of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .7

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Block Diagram of Simultaneous Read/Write

Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 10

Special Package Handling Instructions . . . . . . . 11

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 14

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 15

Table 1. Device Bus Operation . . . . . . . . . . . . . . . . . 15

Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Sector and Sector Groups ...........................................................................................28

Persistent Sector Protection .......................................................................................28

Password Sector Protection ........................................................................................28

WP# Hardware Protection .........................................................................................28

Persistent Sector Protection ............................................................ 29

Persistent Protection Bit (PPB) ..................................................................................29

Persistent Protection Bit Lock (PPB Lock) .............................................................29

Dynamic Protection Bit (DYB) ...................................................................................29

Table 11. Sector Protection Schemes . . . . . . . . . . . . . 30

VersatileI/O™ (V

) Control .............................................................. 15

Requirements for Reading Array Data ........................................... 16

Simultaneous Read/Write

Operations Overview and Restrictions .......................................... 16

Overview ............................................................................................................................16

Restrictions ........................................................................................................................16

Persistent Sector Protection Mode Locking Bit ...........................31

Password Protection Mode .................................................................31

Password and Password Mode Locking Bit ...................................32

64-bit Password ............................................................................................................... 32

Table 2. Bank Assignment for Boot Bank

Sector Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write Protect (WP#) ..........................................................................33

SecSi™ (Secured Silicon) Sector Protection ..................................33

SecSi Sector Protection Bit ................................................................34

Persistent Protection Bit Lock ..........................................................34

Hardware Data Protection ................................................................34

Low V

Write Inhibit .................................................................................................. 34

Write Pulse “Glitch” Protection ................................................................................ 34

Logical Inhibit ................................................................................................................... 35

Power-Up Write Inhibit ................................................................................................ 35

and V

Power-up And Power-down Sequencing ...................................... 35

Simultaneous Read/Write Operations With Zero Latency ..... 17

Table 3. Ordering Option 00 . . . . . . . . . . . . . . . . . . . 17

Table 4. Ordering Option 01 . . . . . . . . . . . . . . . . . . . 17

Writing Commands/Command Sequences ................................... 17

Accelerated Program and Erase Operations ..........................................................18

Autoselect Functions ......................................................................................................18

Table 12. Sector Addresses for Ordering Option 00 . . . 35

Table 13. Sector Addresses for Ordering Option 01 . . . 37

Automatic Sleep Mode (ASM) ........................................................... 18

Standby Mode ...................................................................................................................18

Common Flash Memory Interface (CFI) . . . . . . . 39

Table 14. CFI Query Identification String . . . . . . . . . . 39

Table 15. CFI System Interface String . . . . . . . . . . . . 40

Table 16. Device Geometry Definition . . . . . . . . . . . . 41

Table 17. CFI Primary Vendor-Specific Extended Query 42

RESET#: Hardware Reset Pin ............................................................ 19

Output Disable Mode ........................................................................... 19

Autoselect Mode ................................................................................... 19

Table 5. S29CD016G Autoselect Codes (High Voltage Meth-

od) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Asynchronous Read Operation (Non-Burst) ...............................20

Figure 1. Asynchronous Read Operation . . . . . . . . . . 21

Synchronous (Burst) Read Operation ............................................. 21

Linear Burst Read Operations ........................................................... 21

Table 6. 32- Bit Linear and Burst Data Order . . . . . . . 22

CE# Control in Linear Mode ...................................................................................... 23

ADV# Control In Linear Mode .................................................................................. 23

RESET# Control in Linear Mode ............................................................................... 23

OE# Control in Linear Mode ..................................................................................... 23

IND/WAIT# Operation in Linear Mode ................................................................. 23

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 44

Reading Array Data in Non-burst Mode ...................................... 44

Reading Array Data in Burst Mode ................................................ 44

Read/Reset Command .........................................................................45

Autoselect Command ..........................................................................45

Program Command Sequence ...........................................................45

Accelerated Program Command ..................................................... 46

Unlock Bypass Command Sequence .............................................. 46

Figure 4. Program Operation . . . . . . . . . . . . . . . . . . 47

Unlock Bypass Entry Command ................................................................................. 47

Unlock Bypass Program Command ..........................................................................48

Unlock Bypass Chip Erase Command ......................................................................48

Unlock Bypass CFI Command ....................................................................................48

Unlock Bypass Reset Command ................................................................................48

Table 7. Valid Configuration Register Bit Definition for IND/

WAIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 2. End of Burst Indicator (IND/WAIT#) Timing for

Linear 4-Double-Word Burst Operation . . . . . . . . . . . 24

Burst Access Timing Control ...................................................................................... 24

Initial Burst Access Delay Control ............................................................................24

Chip Erase Command ......................................................................... 48

Sector Erase Command ..................................................................... 49

Figure 5. Erase Operation . . . . . . . . . . . . . . . . . . . . 50

Table 8. Burst Initial Access Delay . . . . . . . . . . . . . . 24

Figure 3. Burst Access Timing . . . . . . . . . . . . . . . . . 25

Burst CLK Edge Data Delivery ................................................................................... 25

Burst Data Hold Control ............................................................................................. 25

Asserting RESET# During A Burst Access .............................................................. 25

Sector Erase and Program Suspend Command .......................... 50

Sector Erase and Program Suspend Operation Mechanics .......51

Table 18. Allowed Operations During Erase/Program Sus-

pend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Configuration Register ........................................................................ 25

Table 9. Configuration Register Definitions . . . . . . . . . 26

Table 10. Configuration Register After Device Reset . . 28

Initial Access Delay Configuration ..................................................28

Sector Erase and Program Resume Command ............................52

Configuration Register Read Command ........................................52

Configuration Register Write Command ......................................52

Common Flash Interface (CFI) Command ....................................52

SecSi Sector Entry Command ............................................................53

S29CD016_00_A4 November 5, 2004

S29CD016G

A d v a n c e

I n f o r m a t i o n

Password Program Command .......................................................... 54

Password Verify Command ............................................................... 54

Password Protection Mode Locking Bit Program Command . 55

Persistent Sector Protection Mode Locking Bit Program Com-

mand ......................................................................................................... 55

SecSi Sector Protection Bit Program Command ........................ 55

PPB Lock Bit Set Command .............................................................. 55

DYB Write Command ........................................................................ 56

Password Unlock Command ............................................................. 56

PPB Program Command ..................................................................... 56

All PPB Erase Command .................................................................... 57

DYB Write .............................................................................................. 57

PPB Lock Bit Set .................................................................................... 57

DYB Status .............................................................................................. 57

PPB Status ............................................................................................... 57

PPB Lock Bit Status .............................................................................. 57

Non-volatile Protection Bit Program And Erase Flow ............. 58

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

matic Sleep Currents) . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 11. Typical I

CC1

vs. Frequency . . . . . . . . . . . . 69

Figure 12. Test Setup . . . . . . . . . . . . . . . . . . . . . . . 70

Table 23. Test Specifications . . . . . . . . . . . . . . . . . . . 70

Key to Switching Waveforms . . . . . . . . . . . . . . . . 70

Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . 70

Figure 13. Input Waveforms and Measurement Levels

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 14. V

and V

Power-up Diagram. . . . . . . . . 71

Table 24. Asynchronous Read Operations . . . . . . . . . . 72

Figure 15. Conventional Read Operations Timings . . . 72

Table 25. Burst Mode Read . . . . . . . . . . . . . . . . . . . . 73

Figure 16. Burst Mode Read (x32 Mode) . . . . . . . . . . 74

Figure 17. Asynchronous Command Write Timing . . . . 75

Figure 18. Synchronous Command Write/Read Timing 75

Table 26. Hardware Reset (RESET#) . . . . . . . . . . . . . 76

Figure 19. RESET# Timings . . . . . . . . . . . . . . . . . . . 76

Figure 20. WP# Timing . . . . . . . . . . . . . . . . . . . . . . 77

Table 27. Erase/Program Operations . . . . . . . . . . . . . 78

Figure 21. Program Operation Timings . . . . . . . . . . . 79

Figure 22. Chip/Sector Erase Operation Timings. . . . . 80

Figure 23. Back-to-back Cycle Timings . . . . . . . . . . . 80

Figure 24. Data# Polling Timings

(During Embedded Algorithms) . . . . . . . . . . . . . . . . 81

Figure 25. Toggle Bit Timings

(During Embedded Algorithms) . . . . . . . . . . . . . . . . 81

Figure 26. DQ2 vs. DQ6 for Erase/Erase Suspend Operations

Figure 27. Synchronous Data Polling Timing/Toggle Bit Tim-

ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 28. Sector Protect/Unprotect Timing Diagram . 83

Table 28. Alternate CE# Controlled Erase/Program Opera-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 29. Alternate CE# Controlled Write Operation Tim-

ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 29. Erase and Programming Performance . . . . . 86

Table 30. PQFP and Fortified BGA Pin Capacitance . . . . 86

Table 19. Memory Array Command Definitions (x32 Mode)

Table 20. Sector Protection Command Definitions (x32

Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 61

DQ7: Data# Polling ............................................................................... 61

Figure 6. Data# Polling Algorithm . . . . . . . . . . . . . . 62

RY/BY#: Ready/Busy# ......................................................................... 63

DQ6: Toggle Bit I .................................................................................. 63

DQ2: Toggle Bit II ................................................................................ 64

Reading Toggle Bits DQ6/DQ2 ........................................................ 64

Figure 7. Toggle Bit Algorithm . . . . . . . . . . . . . . . . . 65

DQ5: Exceeded Timing Limits .......................................................... 66

DQ3: Sector Erase Timer .................................................................. 66

Table 21. Write Operation Status . . . . . . . . . . . . . . . 66

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 67

Figure 8. Maximum Negative Overshoot Waveform . . 67

Figure 9. Maximum Positive Overshoot Waveform . . . 67

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .67

Industrial (I) Devices ...................................................................................................... 67

Extended (E) Devices .................................................................................................... 67

Supply Voltages ...................................................................................................... 67

Supply Voltages ....................................................................................................... 67

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 87

PRQ080–80-Lead Plastic Quad Flat Package 87

LAA080–80-ball Fortified Ball Grid Array (13 x 11

mm) 88

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 22. CMOS Compatible . . . . . . . . . . . . . . . . . . . 68

Figure 10. I

CC1

Current vs. Time (Showing Active and Auto-

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 89

November 5, 2004 S29CD016_00_A4

S29CD016G

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