Intel
®
6 Series Chipset and
Intel
®
C200 Series Chipset
Datasheet
May 2011
Document Number: 324645-006
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2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
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2
Datasheet
Contents
1
Introduction
............................................................................................................ 41
1.1
About This Manual ............................................................................................. 41
1.2
Overview ......................................................................................................... 44
1.2.1
Capability Overview............................................................................. 45
1.3
Intel
®
6 Series Chipset and Intel
®
C200 Series Chipset SKU Definition ..................... 51
Signal Description
................................................................................................... 55
2.1
Direct Media Interface (DMI) to Host Controller ..................................................... 57
2.2
PCI Express* .................................................................................................... 57
2.3
PCI Interface .................................................................................................... 58
2.4
Serial ATA Interface........................................................................................... 60
2.5
LPC Interface.................................................................................................... 63
2.6
Interrupt Interface ............................................................................................ 63
2.7
USB Interface ................................................................................................... 64
2.8
Power Management Interface.............................................................................. 65
2.9
Processor Interface............................................................................................ 69
2.10 SMBus Interface................................................................................................ 69
2.11 System Management Interface............................................................................ 69
2.12 Real Time Clock Interface ................................................................................... 70
2.13 Miscellaneous Signals ........................................................................................ 70
2.14 Intel
®
High Definition Audio Link ......................................................................... 72
2.15 Controller Link .................................................................................................. 73
2.16 Serial Peripheral Interface (SPI) .......................................................................... 73
2.17 Thermal Signals ................................................................................................ 73
2.18 Testability Signals ............................................................................................. 74
2.19 Clock Signals .................................................................................................... 74
2.20 LVDS Signals .................................................................................................... 77
2.21 Analog Display /VGA DAC Signals ........................................................................ 78
2.22 Intel
®
Flexible Display Interface (Intel
®
FDI) ........................................................ 78
2.23 Digital Display Signals........................................................................................ 79
2.24 General Purpose I/O Signals ............................................................................... 82
2.25 Manageability Signals ........................................................................................ 86
2.26 Power and Ground Signals .................................................................................. 87
2.27 Pin Straps ........................................................................................................ 89
2.28 External RTC Circuitry ........................................................................................ 92
PCH
3.1
3.2
3.3
in P S
tates.........................................................................................................
93
Integrated Pull-Ups and Pull-Downs ..................................................................... 93
Output and I/O Signals Planes and States............................................................. 95
Power Planes for Input Signals .......................................................................... 107
2
3
4
PCH and System Clocks
......................................................................................... 113
4.1
Platform Clocking Requirements ........................................................................ 113
4.2
Functional Blocks ............................................................................................ 116
4.3
Clock Configuration Access Overview ................................................................. 117
4.4
Straps Related to Clock Configuration ................................................................ 117
Functional Description
........................................................................................... 119
5.1
DMI-to-PCI Bridge (D30:F0) ............................................................................. 119
5.1.1
PCI Bus Interface.............................................................................. 119
5.1.2
PCI Bridge As an Initiator................................................................... 120
5.1.2.1
Memory Reads and Writes .................................................. 120
5.1.2.2
I/O Reads and Writes ......................................................... 120
5.1.2.3
Configuration Reads and Writes ........................................... 120
5.1.2.4
Locked Cycles ................................................................... 120
5.1.2.5
Target / Master Aborts ....................................................... 120
5.1.2.6
Secondary Master Latency Timer ......................................... 120
5.1.2.7
Dual Address Cycle (DAC)................................................... 121
5.1.2.8
Memory and I/O Decode to PCI ........................................... 121
5.1.3
Parity Error Detection and Generation.................................................. 121
5.1.4
PCIRST# ......................................................................................... 122
5.1.5
Peer Cycles ...................................................................................... 122
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Datasheet
3
5.2
5.3
5.4
5.5
5.6
5.7
5.1.6
PCI-to-PCI Bridge Model ..................................................................... 122
5.1.7
IDSEL to Device Number Mapping........................................................ 123
5.1.8
Standard PCI Bus Configuration Mechanism .......................................... 123
5.1.9
PCI Legacy Mode ............................................................................... 123
PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..................................... 124
5.2.1
Interrupt Generation.......................................................................... 124
5.2.2
Power Management ........................................................................... 125
5.2.2.1
S3/S4/S5 Support .............................................................. 125
5.2.2.2
Resuming from Suspended State.......................................... 125
5.2.2.3
Device Initiated PM_PME Message ........................................ 125
5.2.2.4
SMI/SCI Generation ........................................................... 126
5.2.3
SERR# Generation............................................................................. 126
5.2.4
Hot-Plug .......................................................................................... 126
5.2.4.1
Presence Detection............................................................. 126
5.2.4.2
Message Generation ........................................................... 127
5.2.4.3
Attention Button Detection .................................................. 127
5.2.4.4
SMI/SCI Generation ........................................................... 127
Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 128
5.3.1
GbE PCI Express* Bus Interface .......................................................... 130
5.3.1.1
Transaction Layer............................................................... 130
5.3.1.2
Data Alignment.................................................................. 130
5.3.1.3
Configuration Request Retry Status ...................................... 130
5.3.2
Error Events and Error Reporting ......................................................... 131
5.3.2.1
Data Parity Error ................................................................ 131
5.3.2.2
Completion with Unsuccessful Completion Status.................... 131
5.3.3
Ethernet Interface ............................................................................. 131
5.3.3.1
82579 LAN PHY Interface .................................................... 131
5.3.4
PCI Power Management...................................................................... 132
5.3.4.1
Wake Up ........................................................................... 132
5.3.5
Configurable LEDs ............................................................................. 134
5.3.6
Function Level Reset Support (FLR) ..................................................... 135
5.3.6.1
FLR Steps ......................................................................... 135
LPC Bridge (with System and Management Functions) (D31:F0)............................. 136
5.4.1
LPC Interface .................................................................................... 136
5.4.1.1
LPC Cycle Types................................................................. 137
5.4.1.2
Start Field Definition........................................................... 137
5.4.1.3
Cycle Type / Direction (CYCTYPE + DIR) ............................... 138
5.4.1.4
Size ................................................................................. 138
5.4.1.5
SYNC................................................................................ 138
5.4.1.6
SYNC Time-Out.................................................................. 139
5.4.1.7
SYNC Error Indication ......................................................... 139
5.4.1.8
LFRAME# Usage................................................................. 139
5.4.1.9
I/O Cycles......................................................................... 139
5.4.1.10 Bus Master Cycles .............................................................. 140
5.4.1.11 LPC Power Management ...................................................... 140
5.4.1.12 Configuration and PCH Implications ...................................... 140
DMA Operation (D31:F0) .................................................................................. 141
5.5.1
Channel Priority ................................................................................ 141
5.5.1.1
Fixed Priority ..................................................................... 141
5.5.1.2
Rotating Priority................................................................. 142
5.5.2
Address Compatibility Mode ................................................................ 142
5.5.3
Summary of DMA Transfer Sizes.......................................................... 142
5.5.3.1
Address Shifting When Programmed for 16-Bit I/O Count
by Words .......................................................................... 142
5.5.4
Autoinitialize..................................................................................... 143
5.5.5
Software Commands.......................................................................... 143
LPC DMA ........................................................................................................ 144
5.6.1
Asserting DMA Requests..................................................................... 144
5.6.2
Abandoning DMA Requests ................................................................. 145
5.6.3
General Flow of DMA Transfers............................................................ 145
5.6.4
Terminal Count ................................................................................. 145
5.6.5
Verify Mode ...................................................................................... 146
5.6.6
DMA Request Deassertion................................................................... 146
5.6.7
SYNC Field / LDRQ# Rules .................................................................. 147
8254 Timers (D31:F0) ...................................................................................... 147
5.7.1
Timer Programming ........................................................................... 148
5.7.2
Reading from the Interval Timer.......................................................... 149
4
Datasheet
5.8
5.9
5.10
5.11
5.12
5.13
5.7.2.1
Simple Read ..................................................................... 149
5.7.2.2
Counter Latch Command .................................................... 149
5.7.2.3
Read Back Command ......................................................... 149
8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 150
5.8.1
Interrupt Handling ............................................................................ 151
5.8.1.1
Generating Interrupts......................................................... 151
5.8.1.2
Acknowledging Interrupts ................................................... 151
5.8.1.3
Hardware/Software Interrupt Sequence ................................ 152
5.8.2
Initialization Command Words (ICWx) ................................................. 152
5.8.2.1
ICW1 ............................................................................... 152
5.8.2.2
ICW2 ............................................................................... 153
5.8.2.3
ICW3 ............................................................................... 153
5.8.2.4
ICW4 ............................................................................... 153
5.8.3
Operation Command Words (OCW) ..................................................... 153
5.8.4
Modes of Operation ........................................................................... 153
5.8.4.1
Fully Nested Mode ............................................................. 153
5.8.4.2
Special Fully-Nested Mode .................................................. 154
5.8.4.3
Automatic Rotation Mode (Equal Priority Devices) .................. 154
5.8.4.4
Specific Rotation Mode (Specific Priority) .............................. 154
5.8.4.5
Poll Mode.......................................................................... 154
5.8.4.6
Cascade Mode ................................................................... 155
5.8.4.7
Edge and Level Triggered Mode ........................................... 155
5.8.4.8
End of Interrupt (EOI) Operations ........................................ 155
5.8.4.9
Normal End of Interrupt ..................................................... 155
5.8.4.10 Automatic End of Interrupt Mode ......................................... 155
5.8.5
Masking Interrupts ............................................................................ 156
5.8.5.1
Masking on an Individual Interrupt Request........................... 156
5.8.5.2
Special Mask Mode............................................................. 156
5.8.6
Steering PCI Interrupts...................................................................... 156
Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 157
5.9.1
Interrupt Handling ............................................................................ 157
5.9.2
Interrupt Mapping ............................................................................. 157
5.9.3
PCI / PCI Express* Message-Based Interrupts....................................... 158
5.9.4
IOxAPIC Address Remapping .............................................................. 158
5.9.5
External Interrupt Controller Support................................................... 158
Serial Interrupt (D31:F0) ................................................................................. 159
5.10.1
Start Frame ..................................................................................... 159
5.10.2
Data Frames .................................................................................... 160
5.10.3
Stop Frame ...................................................................................... 160
5.10.4
Specific Interrupts Not Supported Using SERIRQ ................................... 160
5.10.5
Data Frame Format ........................................................................... 161
Real Time Clock (D31:F0)................................................................................. 162
5.11.1
Update Cycles .................................................................................. 162
5.11.2
Interrupts ........................................................................................ 163
5.11.3
Lockable RAM Ranges ........................................................................ 163
5.11.4
Century Rollover ............................................................................... 163
5.11.5
Clearing Battery-Backed RTC RAM....................................................... 163
Processor Interface (D31:F0) ............................................................................ 165
5.12.1
Processor Interface Signals and VLW Messages ..................................... 165
5.12.1.1 A20M# (Mask A20) / A20GATE ............................................ 165
5.12.1.2 INIT (Initialization) ............................................................ 166
5.12.1.3 FERR# (Numeric Coprocessor Error)..................................... 166
5.12.1.4 NMI (Non-Maskable Interrupt)............................................. 167
5.12.1.5 Processor Power Good (PROCPWRGD) .................................. 167
5.12.2
Dual-Processor Issues ....................................................................... 167
5.12.2.1 Usage Differences.............................................................. 167
5.12.3
Virtual Legacy Wire (VLW) Messages ................................................... 167
Power Management ......................................................................................... 168
5.13.1
Features .......................................................................................... 168
5.13.2
PCH and System Power States ............................................................ 168
5.13.3
System Power Planes ........................................................................ 170
5.13.4
SMI#/SCI Generation ........................................................................ 171
5.13.4.1 PCI Express* SCI............................................................... 173
5.13.4.2 PCI Express* Hot-Plug........................................................ 173
5.13.5
C-States .......................................................................................... 173
5.13.6
Dynamic PCI Clock Control (Mobile Only) ............................................. 173
5.13.6.1 Conditions for Checking the PCI Clock .................................. 173
Datasheet
5
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