70V657S12BCI datasheet, PDF - EEWORLD Datasheet

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70V657S12BCI: DescriptionSRAM 32Kx36 STD-PWR, 3.3V DUAL-PORT RAM; Categorystorage; File Size192KB，24 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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70V657S12BCI Overview

SRAM 32Kx36 STD-PWR, 3.3V DUAL-PORT RAM

70V657S12BCI Parametric

Parameter Name	Attribute value
Product Category	SRAM
Manufacturer	IDT (Integrated Device Technology, Inc.)
RoHS	No
Memory Size	1 Mbit
Organization	32 k x 36
Access Time	12 ns
Interface Type	Parallel
Supply Voltage - Max	3.45 V
Supply Voltage - Min	3.15 V
Supply Current - Max	515 mA
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	CABGA-256
Packaging	Tray
Height	1.4 mm
Length	17 mm
Memory Type	SDR
Moisture Sensitive	Yes
Operating Temperature Range	- 40 C to + 85 C
Factory Pack Quantity	6
Type	Asynchronous
Width	17 mm

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HIGH-SPEED 3.3V

IDT70V659/58/57S

128/64/32K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

Features

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 10/12/15ns (max.)

– Industrial: 12/15ns (max.)

Dual chip enables allow for depth expansion without

external logic

IDT70V659/58/57 easily expands data bus width to 72 bits

or more using the Master/Slave select when cascading

more than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

◆

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Supports JTAG features compliant to IEEE 1149.1

LVTTL-compatible, single 3.3V (±150mV) power supply for

core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 208-pin Plastic Quad Flatpack, 208-ball fine

pitch Ball Grid Array, and 256-ball Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Functional Block Diagram

BBBB

EEEE

3 2 10

RRRR

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout9-17_R

Dout18-26_L Dout18-26_R

Dout27-35_L Dout27-35_R

128/64/32K x 36

MEMORY

ARRAY

I/O

0L-

I/O

35L

Di n_L

Di n_R

I/O

0R -

I/O

35R

16 L(1)

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

16R(1)

R/W

BUSY

L(2,3)

SEM

INT

L(3)

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

M/S

BUSY

R(2,3)

SEM

INT

R(3)

TDI

TDO

JTAG

TMS

TCK

TRST

4869 drw 01

NOTES:

1. A

is a NC for IDT70V658. Also, Addresses A

and A

are NC's for IDT70V657.

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

OCTOBER 2008

DSC-4869/7

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