PCA9547
8-channel I
2
C-bus multiplexer with reset
Rev. 4 — 1 April 2014
Product data sheet
1. General description
The PCA9547 is an octal bidirectional translating multiplexer controlled by the I
2
C-bus.
The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only one
SCx/SDx channel can be selected at a time, determined by the contents of the
programmable control register. The device powers up with Channel 0 connected, allowing
immediate communication between the master and downstream devices on that channel.
An active LOW reset input allows the PCA9547 to recover from a situation where one of
the downstream I
2
C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets
the I
2
C-bus state machine causing all the channels to be deselected, except Channel 0 so
that the master can regain control of the bus.
The pass gates of the multiplexers are constructed such that the V
DD
pin can be used to
limit the maximum high voltage which will be passed by the PCA9547. This allows the use
of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate
with 5 V parts without any additional protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features and benefits
1-of-8 bidirectional translating multiplexer
I
2
C-bus interface logic; compatible with SMBus standards
Active LOW RESET input
3 address pins allowing up to 8 devices on the I
2
C-bus
Channel selection via I
2
C-bus, one channel at a time
Power-up with all channels deselected except Channel 0 which is connected
Low R
on
multiplexers
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO24, TSSOP24, HVQFN24
NXP Semiconductors
PCA9547
8-channel I
2
C-bus multiplexer with reset
3. Ordering information
Table 1.
Ordering information
Topside
marking
PCA9547D
PCA9547PW
9547
Package
Name
SO24
TSSOP24
HVQFN24
Description
plastic small outline package; 24 leads; body width 7.5 mm
plastic thin shrink small outline package; 24 leads; body width
4.4 mm
Version
SOT137-1
SOT355-1
Type number
PCA9547D
PCA9547PW
PCA9547BS
plastic thermal enhanced very thin quad flat package; no leads; SOT616-1
24 terminals; body 4
4
0.85 mm
3.1 Ordering options
Table 2.
Ordering options
Orderable part
number
PCA9547D,112
PCA9547D,118
PCA9547PW
PCA9547PW,112
PCA9547PW,118
PCA9547BS
PCA9547BS,118
Package
Packing method
Minimum
order
quantity
1200
1000
1575
2500
6000
Temperature range
Type number
PCA9547D
SO24
SO24
TSSOP24
TSSOP24
HVQFN24
Standard marking
* IC’s tube - DSC bulk pack
Reel 13” Q1/T1
*Standard mark SMD
Standard marking
* IC’s tube - DSC bulk pack
Reel 13” Q1/T1
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
PCA9547
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 1 April 2014
2 of 30
NXP Semiconductors
PCA9547
8-channel I
2
C-bus multiplexer with reset
5. Pinning information
5.1 Pinning
A0
A1
RESET
SD0
SC0
SD1
SC1
SD2
SC2
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A2
20 SC7
19 SD7
18 SC6
17 SD6
16 SC5
15 SD5
14 SC4
13 SD4
002aaa958
A0
A1
RESET
SD0
SC0
SD1
SC1
SD2
SC2
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A2
20 SC7
19 SD7
18 SC6
17 SD6
16 SC5
15 SD5
14 SC4
13 SD4
002aaa959
PCA9547D
PCA9547PW
SD3 10
SC3 11
V
SS
12
SD3 10
SC3 11
V
SS
12
Fig 2.
Pin configuration for SO24
24 RESET
Fig 3.
Pin configuration for TSSOP24
20 SDA
23 A1
SD0
SC0
SD1
SC1
SD2
SC2
1
2
3
4
5
6
SD4 10
SC4 11
SD5 12
7
8
9
22 A0
terminal 1
index area
19 SCL
18 A2
17 SC7
16 SD7
15 SC6
14 SD6
13 SC5
002aaa960
PCA9547BS
SD3
SC3
Transparent top view
Fig 4.
Pin configuration for HVQFN24 (transparent top view)
PCA9547
All information provided in this document is subject to legal disclaimers.
V
SS
21 V
DD
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 1 April 2014
4 of 30
NXP Semiconductors
PCA9547
8-channel I
2
C-bus multiplexer with reset
5.2 Pin description
Table 3.
Symbol
A0
A1
RESET
SD0
SC0
SD1
SC1
SD2
SC2
SD3
SC3
V
SS
SD4
SC4
SD5
SC5
SD6
SC6
SD7
SC7
A2
SCL
SDA
V
DD
[1]
Pin description
Pin
SO24, TSSOP24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
HVQFN24
22
23
24
1
2
3
4
5
6
7
8
9
[1]
10
11
12
13
14
15
16
17
18
19
20
21
address input 0
address input 1
active LOW reset input
serial data output 0
serial clock output 0
serial data output 1
serial clock output 1
serial data output 2
serial clock output 2
serial data output 3
serial clock output 3
supply ground
serial data output 4
serial clock output 4
serial data output 5
serial clock output 5
serial data output 6
serial clock output 6
serial data output 7
serial clock output 7
address input 2
serial clock line
serial data line
supply voltage
Description
HVQFN24 package die supply ground is connected to both the V
SS
pin and the exposed center pad. The
V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
PCA9547
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 1 April 2014
5 of 30
Embedded System
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